MM908E625ACDWB Freescale Semiconductor, MM908E625ACDWB Datasheet - Page 39

• Manufacturer Part Number: MM908E625ACDWB
• Description: IC QUAD HALF BRDG MCU/LIN 54SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MM908E625ACDWB

• Applications: Automotive Mirror Control
• Core Processor: HC08
• Program Memory Type: FLASH (16 kB)
• Controller Series: 908E
• Ram Size: 512 x 8
• Interface: SCI, SPI
• Number Of I /o: 13
• Voltage - Supply: 8 V ~ 18 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 54-SOIC (0.300", 7.50mm Width) Exposed Pad
• Program Memory Size: 16 KB
• Number Of Programmable I/os: 54
• Number Of Timers: 16
• Operating Supply Voltage: - 18 V to + 28 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Flag Register.
AUTONOMOUS WATCHDOG (AWD)
functions:
AWDCTL Register is set. If these bits are cleared, the AWD
oscillator is disabled and the watchdog switched off.
WATCHDOG
setting the AWDRE bit, watchdog functionality in RUN mode
is activated. Once this function is enabled, it is not possible to
disable it via software.
system reset is initiated. Operations of the watchdog function
cease in STOP mode. Normal operation will be continued
when the system is back to RUN mode.
counter must be reset before it reaches the end value. This is
done by a write to the AWDRST bit in the AWDCTL Register.
PERIODIC INTERRUPT
enabled by setting the AWDIE bit in the AWDCTL Register. If
AWDIE is set, the AWD wakes up the system after a fixed
period of time. This time period can be selected with bit
AWDR in the AWDCTL Register.
CYCLIC WAKE-UP
mode. If this feature is enabled, the selected Hall-effect
sensor input pins are switched on and sensed. If a “1” is
detected on one of these inputs and the interrupt for the Hall-
effect sensors is enabled, a system wake-up is performed.
(Switch on main voltage regulator and assert
microcontroller).
Overtemperature Status Bit (HTF)
Analog Integrated Circuit Device Data
Freescale Semiconductor
This read-only bit is a copy of the HTF bit in the Interrupt
• 1 = Overtemperature condition has occurred
• 0 = No overtemperature condition has occurred
The Autonomous Watchdog module consists of three
• Watchdog function for the CPU in RUN mode
• Periodic interrupt function in STOP mode
• Cyclic wake-up function in STOP mode
The AWD is enabled if AWDIE, AWDRE, or AWDCC in the
The watchdog function is only available in RUN mode. On
If the timer reaches end value and AWDRE is set, a
To prevent a watchdog reset, the watchdog timeout
Periodic interrupt is only available in STOP mode. It is
The cyclic wake-up feature is only available in STOP
IRQ_A
to the
AUTONOMOUS WATCHDOG CONTROL
REGISTER (AWDCTL)
timeout period. AWDRST always reads 0. Reset clears
AWDRST bit.
Autonomous Watchdog Reset Enable Bit (AWDRE)
reset on the
RUN mode. AWDRE is one-time setable (write once) after
each reset. Reset clears the AWDRE bit.
Autonomous Watchdog timeout flag, AWFD.
asserted when the device is in STOP mode. Reset clears the
AWDIE bit.
Hall-effect sensor and the analog inputs. Reset clears the
AWDCC bit.
Watchdog has timed out. Clear AWDF by writing a Logic [1]
to AWDF. Clearing AWDF also resets the AWD counter and
starts a new timeout period. Reset clears the AWDF bit.
Writing a Logic [0] to AWDF has no effect.
Autonomous Watchdog Reset Bit (AWDRST)
Autonomous Watchdog Interrupt Enable Bit (AWDIE)
Autonomous Watchdog Cyclic Check (AWDCC)
Autonomous Watchdog Timeout Flag Bit (AWDF)
Bits
Reset
Write
Read
This write-only bit resets the Autonomous Watchdog
• 1 = Reset AWD and restart timeout period
• 0 = No effect
This read/write bit enables resets on AWD time-outs. A
• 1 = Autonomous watchdog enabled
• 0 = Autonomous watchdog disabled
This read/write bit enables CPU interrupts by the
• 1 = CPU interrupt requests from AWDF enabled
• 0 = CPU interrupt requests from AWDF disabled
This read/write bit enables the cyclic check of the two-pin
• 1 = Cyclic check of the Hall-effect sensor and analog
• 0 = No cyclic check of the Hall-effect sensor and analog
This read/write flag is set when the Autonomous
• 1 = AWD has timed out
• 0 = AWD has not yet timed out
port
port
Register Name and Address: AWDCTL - $0a
7
0
0
RST_A
6
0
0
is only asserted when the device is in
AWDRS
5
T
0
0
LOGIC COMMANDS AND REGISTERS
FUNCTIONAL DEVICE OPERATION
AWDR
4
E
0
AWDI
3
E
0
AWDC
2
C
0
IRQ_A
AWDF
1
0
is only
908E625
AWD
R
0
0
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