ISP1161A1BMGA STEricsson, ISP1161A1BMGA Datasheet - Page 18
ISP1161A1BMGA
Manufacturer Part Number
ISP1161A1BMGA
Description
Manufacturer
STEricsson
Datasheet
1.ISP1161A1BMGA.pdf
(137 pages)
Specifications of ISP1161A1BMGA
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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ISP1161A1_5
Product data sheet
Fig 18. DMA transfer in burst mode.
RD or WR
D [ 15:0 ]
DREQ
DACK
EOT
N = 1/2 byte count of transfer data, K = number of cycles/burst.
8.6.1 Pin configuration
8.6 Interrupts
data #1
In both figures, the hardware is configured such that DREQ is active HIGH and DACK is
active LOW.
The ISP1161A1 has separate interrupt request pins for the USB HC (INT1) and the
USB DC (INT2).
The interrupt output signals have four configuration modes:
Mode 0
Mode 1
Mode 2
Mode 3
Figure 19
HcHardwareConfiguration register (see
enable the signals.
shows these four interrupt configuration modes. They are programmable via the
data #K
Level trigger, active LOW (default at power-up)
Level trigger, active HIGH
Edge trigger, active LOW
Edge trigger, active HIGH.
data #(K+1)
Rev. 05 — 29 September 2009
data #2K
Section
USB single-chip host and device controller
10.4.1), which is also used to disable or
data #(N−K+1)
ISP1161A1
data #N
© ST-ERICSSON 2009. All rights reserved.
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