ISP1161A1BMGA STEricsson, ISP1161A1BMGA Datasheet - Page 99

• Manufacturer Part Number: ISP1161A1BMGA
• Manufacturer: STEricsson

Specifications of ISP1161A1BMGA

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

ISP1161A1_5
Product data sheet
13.2.2 DcEndpointStatus register (R: 50H–5FH)
Code (Hex): 01 to 0F — write (control IN, endpoint 1 to 14)
Code (Hex): 10, 12 to 1F — read (control OUT, endpoint 1 to 14)
Transaction — write/read maximum (M + 1) words (isochronous endpoint: N ≤ 1023,
bulk/interrupt endpoint: N ≤ 32)
The data in the endpoint FIFO must be organized as shown in
endpoint FIFO access is given
Table 90.
Table 91.
Remark: There is no protection against writing or reading past a buffer’s boundary or
against writing into an OUT buffer or reading from an IN buffer. Any of these actions could
cause an incorrect operation. Data residing in an OUT buffer are only meaningful after a
successful transaction. Exception: during DMA access of a double-buffered endpoint, the
buffer pointer automatically points to the secondary buffer after reaching the end of the
primary buffer.
This command is used to read the status of an endpoint FIFO. The command accesses
the DcEndpointStatus register, the bit allocation of which is shown in
the DcEndpointStatus register will clear the interrupt bit set for the corresponding endpoint
in the DcInterrupt register (see
All bits of the DcEndpointStatus register are read-only. Bit EPSTAL is controlled by the
Stall/Unstall commands and by the reception of a SETUP token (see
Code (Hex): 50 to 5F — read (control OUT, control IN, endpoint 1 to 14)
Transaction — read 1 word
Word #
0 (lower byte)
0 (upper byte)
1 (lower byte)
1 (upper byte)
:
M = (N + 1)/2
A0
1
0
0
0
:
Phase
command
data
data
data
:
Endpoint FIFO organization
Example of endpoint FIFO access
Rev. 05 — 29 September 2009
Description
packet length (lower byte)
packet length (upper byte)
data byte 1
data byte 2
:
data byte N
Bus lines
D[7:0]
D[15:8]
D[15:0]
D[15:0]
D[15:0]
:
Table
Table
91.
108).
Word #
-
-
0
1
2
:
USB single-chip host and device controller
Description
command code (00H to 1FH)
ignored
packet length
data word 1 (data byte 2, data byte 1)
data word 2 (data byte 4, data byte 3)
:
Table
ISP1161A1
© ST-ERICSSON 2009. All rights reserved.
90. An example of
Table
Section
92. Reading
13.2.3).
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