ISP1161A1BMGA STEricsson, ISP1161A1BMGA Datasheet - Page 89

• Manufacturer Part Number: ISP1161A1BMGA
• Manufacturer: STEricsson

Specifications of ISP1161A1BMGA

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

13. DC commands and registers
Table 75.
ISP1161A1_5
Product data sheet
Name
Initialization commands
Write Control OUT
Configuration
Write Control
IN Configuration
Write Endpoint
n Configuration (n = 1 to 14)
Read Control OUT
Configuration
Read Control
IN Configuration
Read Endpoint
n Configuration (n = 1 to 14)
Write/Read Device Address
Write/Read Mode register
Write/Read Hardware
Configuration
Write/Read
DcInterruptEnable register
Write/Read DMA
Configuration
Write/Read DMA Counter
DC command and register summary
The functions and registers of the ISP1161A1’s DC are accessed via commands, which
consist of a command code followed by optional data bytes (read or write action). An
overview of the available commands and registers is given in
A complete access consists of two phases:
As the ISP1161A1 DC’s data bus is 16 bits wide:
1. Command phase: when address bit A0 = 1, the DC interprets the data on the lower
2. Data phase (optional): when address bit A0 = 0, the DC transfers the data on the
•
•
•
byte of the bus (bits D7 to D0) as a command code. Commands without a data phase
are executed immediately.
bus to or from a register or endpoint FIFO. Multi-byte registers are accessed least
significant byte/word first.
The upper byte (bits D15 to D8) in command phase, or the undefined byte in data
phase and is ignored.
The access of registers is word-aligned: byte access is not allowed.
If the packet length is odd, the upper byte of the last word in an IN endpoint buffer is
not transmitted to the host. When reading from an OUT endpoint buffer, the upper
byte of the last word must be ignored by the firmware. The packet length is stored in
the first 2 bytes of the endpoint buffer.
Destination
DcEndpointConfiguration
register endpoint 0 OUT
DcEndpointConfiguration
register endpoint 0 IN
DcEndpointConfiguration
register endpoint 1 to 14
DcEndpointConfiguration
register endpoint 0 OUT
DcEndpointConfiguration
register endpoint 0 IN
DcEndpointConfiguration
register endpoint 1 to 14
DcAddress register
DcMode register
DcHardwareConfiguration
register
DcInterruptEnable register
DcDMAConfiguration
register
DcDMACounter register
Rev. 05 — 29 September 2009
Code
(Hex)
20
21
22 to 2F
30
31
32 to 3F
B6/B7
B8/B9
BA/BB
C2/C3
F0/F1
F2/F3
USB single-chip host and device controller
Transaction
write 1 word
write 1 word
write 1 word
read 1 word
read 1 word
read 1 word
write/read 1 word
write/read 1 word
write/read 1 word
write/read 2 words
write/read 1 word
write/read 1 word
[1]
Table
Reference
Section 13.1.1 on page 91
Section 13.1.2 on page 92
Section 13.1.3 on page 92
Section 13.1.4 on page 93
Section 13.1.5 on page 95
Section 13.1.6 on page 96
Section 13.1.7 on page 97
ISP1161A1
75.
© ST-ERICSSON 2009. All rights reserved.
89 of 137