ISP1161A1BMGA STEricsson, ISP1161A1BMGA Datasheet - Page 85

• Manufacturer Part Number: ISP1161A1BMGA
• Manufacturer: STEricsson

Specifications of ISP1161A1BMGA

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

ISP1161A1_5
Product data sheet
12.2 8237 compatible mode
Table 70.
The 8237 compatible DMA mode is selected by clearing bit DAKOLY in the
DcHardwareConfiguration register (see
shown in
Table 71.
The DMA subsystem of an IBM compatible PC is based on the Intel 8237 DMA controller.
It operates as a ‘fly-by’ DMA controller: the data is not stored in the DMA controller, but it
is transferred between an I/O port and a memory address. A typical example of the
ISP1161A1’s DC in 8237 compatible DMA mode is given in
The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and
DACK (DMA Acknowledge). General control signals are HRQ (Hold Request) and HLDA
(Hold Acknowledge). The bus operation is controlled via MEMR (Memory read), MEMW
(Memory write), IOR (I/O read) and IOW (I/O write).
The following example shows the steps which occur in a typical DMA transfer:
Endpoint
identifier
11
12
13
14
Symbol
DREQ2
DACK2
EOT
RD
WR
Fig 40. ISP1161A1’s device controller in 8237 compatible DMA mode.
Table
Endpoint selection for DMA transfer
8237 compatible mode: pin functions
Description
DC’s DMA request
DC’s DMA acknowledge I
end of transfer
read strobe
write strobe
CONTROLLER
ISP1161A1
71.
DEVICE
EPIDX[3:0]
1100
1101
1110
1111
D0 to D15
Rev. 05 — 29 September 2009
DREQ2
DACK2
WR
RD
I/O
O
I
I
I
RAM
Transfer direction
EPDIR = 0
OUT: read
OUT: read
OUT: read
OUT: read
Table
USB single-chip host and device controller
MEMR
MEMW
DREQ
DACK
IOR
IOW
82). The pin functions for this mode are
CONTROLLER
…continued
Function
ISP1161A1’s DC requests a DMA transfer
DMA controller confirms the transfer
DMA controller terminates the transfer
instructs the ISP1161A1’s DC to put data on
the bus
instructs the ISP1161A1’s DC to get data
from the bus
DMA
8237
HLDA
HRQ
Figure
EPDIR = 1
IN: write
IN: write
IN: write
IN: write
ISP1161A1
40.
HRQ
HLDA
© ST-ERICSSON 2009. All rights reserved.
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