ISP1161A1BMGA STEricsson, ISP1161A1BMGA Datasheet - Page 86

• Manufacturer Part Number: ISP1161A1BMGA
• Manufacturer: STEricsson

Specifications of ISP1161A1BMGA

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

ISP1161A1_5
Product data sheet
12.3 DACK-only mode
10. The 8237 de-asserts the DACK output indicating that the ISP1161A1’s DC must stop
11. The 8237 places the bus control signals (MEMR, MEMW, IOR and IOW) and the
12. The CPU acknowledges control of the bus by de-asserting HLDA. After activating the
For a typical bulk transfer the above process is repeated, once for each byte. After each
byte the address register in the DMA controller is incremented and the byte counter is
decremented. When using 16-bit DMA the number of transfers is 32, and address
incrementing and byte counter decrementing is done by 2 for each word.
The DACK-only DMA mode is selected by setting bit DAKOLY in the
DcHardwareConfiguration register (see
shown in
given in
Table 72.
Symbol
DREQ2
DACK2
1. The ISP1161A1’s DC receives a data packet in one of its endpoint FIFOs; the packet
2. The ISP1161A1’s DC asserts the DREQ2 signal requesting the 8237 for a DMA
3. The 8237 asks the CPU to release the bus by asserting the HRQ signal.
4. After completing the current instruction cycle, the CPU places the bus control signals
5. The 8237 now sets its address lines to 1234H and activates the MEMW and IOR
6. The 8237 asserts DACK to inform the ISP1161A1’s DC that it will start a DMA
7. The ISP1161A1’s DC now places the word to be transferred on the data bus lines,
8. The 8237 waits one DMA clock period and then de-asserts MEMW and IOR. This
9. The ISP1161A1’s DC de-asserts the DREQ2 signal to indicate to the 8237 that DMA
must be transferred to memory address 1234H.
transfer.
(MEMR, MEMW, IOR and IOW) and the address lines in three-state and asserts
HLDA to inform the 8237 that it has control of the bus.
control signals.
transfer.
because its RD signal was asserted by the 8237.
latches and stores the word at the desired memory location. It also informs the
ISP1161A1’s DC that the data on the bus lines has been transferred.
is no longer needed. In Single cycle mode this is done after each word, in Burst
mode following the last transferred word of the DMA cycle.
placing data on the bus.
address lines in three-state and de-asserts the HRQ signal, informing the CPU that it
has released the bus.
bus control lines (MEMR, MEMW, IOR and IOW) and the address lines, the CPU
resumes the execution of instructions.
Figure
Table
DACK-only mode: pin functions
Description
DC’s DMA request
DC’s DMA acknowledge I
72. A typical example of the ISP1161A1’s DC in DACK-only DMA mode is
41.
Rev. 05 — 29 September 2009
I/O
O
Table
USB single-chip host and device controller
82). The pin functions for this mode are
Function
ISP1161A1 DC requests a DMA transfer
DMA controller confirms the transfer; also
functions as data strobe
ISP1161A1
© ST-ERICSSON 2009. All rights reserved.
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