PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 112

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
vided to synchronize message passing to other
PNX1300 message receivers.
7.4.1
The EVO provides the following key functions.
• Continuous digital video output of PAL or NTSC for-
• Transmission of YUV 4:2:2 co-sited pixel data across
• Supports the nominal PAL/NTSC data rate of 27
• Custom video formats can be programmed with
• Support for video images in planar YUV 4:2:2 co-
• Optional 129-level alpha blending. Graphics overlay
• Optional horizontal 2X upscaling of the video image
• In data-streaming mode, the EVO acts as a high
• In message-passing mode, the EVO can send mes-
• For diagnostic purposes, EVO output data can be
7.4.2
The EVO normally supplies continuous video data to its
outputs. The EVO is programmed and started by the
PNX1300 DSPCPU. The EVO issues an interrupt to the
DSPCPU at the end of each transmitted field, and/or at a
programmable vertical position in the field. The DSPCPU
updates the EVO video image data pointers with pointers
to the next field during the vertical blanking interval so as
to maintain continuous video output. During video output,
7-2
1.
mat data according to CCIR 601.
a standard 8-bit parallel CCIR 656
Embedded SAV and EAV synchronization codes and
separate sync control signals compatible with Philips
DENC encoders are available.
MB/sec. (13. 5 Mpix/sec.), or any byte data rate up to
an 81-MHz EVO clock.
frames or fields of up to 4095 lines of up to 4095 pix-
els, subject only to the data rate limitation above.
sited, planar YUV 4:2:2 interspersed, or planar YUV
4:2:0 memory formats.
image is in pixel-packed YUV 4:2:2+α format, and is
alpha blended on top of the video image. Each pixel
has a 1-bit alpha, which selects one of two global 8-
bit alpha values which provide 129 layers of transpar-
ency. With overlay enabled, the output byte data rate
is limited to 45% of the SDRAM clock, or up to an 81-
MHz EVO clock, whichever is smaller.
for display. The overlay is always in display format.
bandwidth continuous-output data channel. The byte
data rate is limited to an 81-MHz EVO clock.
sages from 1 word (4 bytes) up to 16 MB. The byte
data rate is limited to an 81-MHz EVO clock.
internally looped back to the VI port. This is con-
trolled by the VI DIAGMODE bit.
Refer to CCIR recommendation 656: Interfaces for dig-
ital component video signals in 525 line and 625 line
television systems. Recommendation 656 is included in
the Philips Desktop Video Data Handbook.
Detailed Feature Descriptions
Summary of Operation
PRELIMINARY SPECIFICATION
1
interface.
the EVO supplies embedded CCIR 656 SAV (Start Ac-
tive Video) and EAV (End Active Video) sync codes and
optionally supplies horizontal and frame sync signals.
The EVO can either supply pixel clock and horizontal and
frame timing signals or it can lock to external timing sig-
nals such as those supplied by a Philips SAA7125 DENC
digital encoder or similar sync source.
7.5
Table 7-1
Figure
connections for commonly-used external devices that in-
terface to the EVO.
The most common way to generate analog video is
shown in
Encoder (DENC) can be programmed to derive sync ei-
ther from the VO_DATA stream EAV/SAV codes, or from
its RCV1/2 pins.
Figure 7-2
dard CCIR 656 interface can be created. In certain pro-
fessional applications, serial D1 video is also used. In
that case, the EVO can be connected to a Gennum
GS9022 Digital Video Serializer or similar part (not
shown).
Figure 7-3
nected to the VI unit of a second PNX1300.
Figure 7-1. EVO connected to a digital video encod-
er (DENC).
Figure 7-2. EVO connected to a CCIR 656 video-
output connector.
7-1,
PNX1300
INTERFACE
PNX1300
VO_DATA[7:0]
Figure
VO_DATA[7:0]
illustrates how a byte-parallel ECL-level stan-
lists the interface pins of the EVO unit.
(HS) VO_IO1
(FS) VO_IO2
shows the EVO unit of one PNX1300 con-
Figure
VO_CLK
VO_CLK
7-1. In this setup, an SAA7125 Digital
7-2, and
8
1
TTL to ECL
Philips Semiconductors
Figure 7-3
MP[7:0]
RCV1
RCV2
LLC
16
2
“D” Connector
Subminiature
CCIR 656
SAA7125
illustrate typical
Data A,B[7:0]
Clock A,B