PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 253

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
16.7
The I
below. In hardware operating mode, the IIC__SCL exter-
nal clock is derived by division from the BOOT_CLK pin
on PNX1300. The BOOT_CLK pin is normally connected
to TRI_CLKIN. The IIC__SCL clock divider value is de-
termined at boot time and cannot be changed thereafter.
The value chosen depends on the first byte read from the
EEPROM, as described in
dure Common to Both Autonomous and Host-Assisted
Bootstrap.”
The PNX1300 I
in response to slaves that need to slow down byte trans-
fer. This mechanism of slowing SCL in response to a
slave is called ‘clock stretching.’ This clock stretching is
accomplished by the slave by holding the SCL line ‘low’
Figure 16-5. I
2
TRI_RESET#
C hardware block diagram is shown in
I
BOOTCLKIN
2
C CLOCK RATE GENERATION
PAD
2
.
. 4
2
C block diagram
C block is able to ‘stretch’ the SCL clock
(eeprom image
Byte0,bit0)
PAD
I
ATE
boot_sclk
Section 13.2.1, “Boot Proce-
Gen Prog
I
2
IIC_SCL
Reset
C Clock
Logic
Boot S/M
and Logic
PAD
cpu-arst
Figure 16-5
sync
sclk
controls
cpu-arst
Boot Address
Boot Data
level S/M
sclk
0
n
I
2
C low
1
controls
controls
Table 16-8. I
after completion of a byte transfer and acknowledge se-
quence. Clock stretching is always enabled.
PRELIMINARY SPECIFICATION
00 (100 MHz)
00
01 (75 MHz)
01
10 (50 MHz)
10
11 (33 MHz)
11
BOOT_CLK
controls
S/M
I
I/F
2
bits
C
Register
Data
2
Serializer/Deserializer
C speed and EEPROM byte 0
0 (100 kHz)
1 (400 kHz)
0 (100 kHz)
1 (400 kHz)
0 (100 kHz)
1 (400 kHz)
0 (100 kHz)
1 (400 kHz)
cpu-arst
speed bit
EEPROM
boot addr
IIC_SDA
PAD
Register
IIC_AR reg
Addr
0 1
Data Hiway
divider
value
1008
256
192
128
336
752
512
96
IIC_DR reg
I2C Interface
99.2 kHz
390.6 kHz
99.7 kHz
390.6 kHz
97.6 kHz
390.6 kHz
98.2 kHz
343.8 kHz
actual I
Boot
Data
speed
2
16-7
C