PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 154

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
Table 9-13. AO MMIO Control Fields
9.11
The AO_TSTAMP MMIO register provides a 32-bit
timestamp value that contains the CCCOUNT time value
at which the last sample of the last DMA buffer transmit-
ted was sent across the SD output pin. This value is
available for software inspection (read-only) in the inter-
rupt handler for BUFx_EMPTY.
9-10
RESET
TRANS_ENABLE
SLEEPLESS
BUF1_INTEN
BUF2_INTEN
HBE_INTEN
UDR_INTEN
ACK1
ACK2
ACK_HBE
ACK_UDR
Field Name
TIMESTAMP
Resets the audio-out logic. See
9.9, “Audio Out Operation”
tion of the recommended procedure.
Transmission Enable flag.
0 ⇒ (RESET default) AO inactive.
1 ⇒ AO transmits samples and acts as
Do NOT change the POLARITY bit while
transmission is enabled.
0 ⇒ (power up default) AO goes into
1 ⇒ AO continues operation when
Buffer 1 Empty Interrupt Enable.
0 ⇒ (default) no interrupt
1 ⇒ interrupt (SOURCE 12) if buffer 1
Buffer 2 Empty Interrupt Enable.
0 ⇒ (default) no interrupt
1 ⇒ interrupt (SOURCE 12) if buffer 2
HBE Interrupt Enable.
0 ⇒ (default) no interrupt
1 ⇒ interrupt (SOURCE 12) if a highway
UNDERRUN Interrupt Enable.
0 ⇒ (default) no interrupt
1 ⇒ interrupt (SOURCE 12) if an
• Write a 1 to clear the BUF1_EMPTY flag
• ACK1 always reads 0.
• Write a 1 to clear the BUF2_EMPTYflag
• ACK2 always reads 0.
• Write a 1 to clear the HBE flag and
• remove any pending HBE interrupt
• ACK_HBE always reads as 0.
• Write a 1 to clear the UNDERRUN flag
• ACK_UDR always reads 0.
and remove any pending BUF1_EMPTY
interrupt request.
and remove any pending BUF2_EMPTY
interrupt request.
request.
and remove any pending UNDERRUN
interrupt request.
PRELIMINARY SPECIFICATION
DMA master to read samples from
local SDRAM.
power-down mode if PNX1300 goes
to global powerdown mode.
PNX1300 goes to global powerdown
mode. Samples are read from mem-
ory as needed, and AO interrupts,
when enabled, will wake up the
DSPCPU.
empty
empty
bandwidth error occurs.
UNDERRUN error occurs
Description
for a descrip-
Section
The implementation involves an internal DSPCPU clock
cycle counter that is reset to have the same value as the
DSPCPU CCCOUNT register. It is guaranteed to be in
sync with the 32 LSB of CCCOUNT provided that PC-
SW.CS=1.
9.12
The AO unit enters powerdown state whenever
PNX1300 is put in global powerdown mode, except if the
SLEEPLESS bit in AO_CTL is set. In the latter case, the
block continues DMA operation and will wake up the
DSPCPU whenever an interrupt is generated. The inter-
nal timestamp counter never powers down to ensure that
it remains synchronous with CCCOUNT.
The AO unit can be separately powered down by setting
a bit in the BLOCK_POWER_DOWN register. Refer to
Chapter 21, “Power Management.”
If the block enters powerdown state, AO_SCK, AO_SDx,
and AO_WS hold their value stable. AO_OSCLK contin-
ues to provide a D/A converter clock. The signals resume
their original transitions at the point where they were in-
terrupted once the system wakes up. The external D/A
converter subsystem is most likely confused by this be-
havior, hence it is recommended AO unit to be stopped
(by negating TRANS_ENABLE) before block level pow-
erdown is started, or that SLEEPLESS mode is used
when global powerdown is activated.
9.13
The AO unit uses an internal 64-byte buffer as well as an
output holding register that contains a single mono sam-
ple or single stereo sample pair. Under normal operation,
the internal buffer is refreshed from SDRAM fast enough
to avoid any missing samples, while data is being emit-
ted from the holding register. If the highway arbiter is set
up with an insufficient latency guarantee, the situation
can arise that the 64-byte buffer is not refilled and the
holding register is exhausted by the time a new output
sample is due. In that case the HBE error is raised. The
last sample for each channel will be repeated until the
buffer is refreshed. The HBE condition is sticky, and can
only be cleared by an explicit ACK_HBE. This condition
indicates an incorrect setting of the highway bandwidth
arbiter.
Given a sample rate f
val T (in ns), the arbiter should be set to have a latency
of at most T-20 ns for all modes. The latency for 4,6 and
8 channel modes can be computed as if the system is op-
erating in stereo mode with a 2x, 3x respectively 4x sam-
ple rate.
Table 9-14
a number of common operating modes. The right most
column in illustrates the nature of the resulting 64-byte
highway requests. Is not necessary to compute arbiter
settings, but they may be used to compute bus availabil-
ity in a given interval.
Refer to
programming.
POWERDOWN AND SLEEPLESS
HIGHWAY LATENCY AND HBE
Chapter 20, “Arbiter,”
shows the required arbiter latency settings for
s
, and an associated sample inter-
Philips Semiconductors
for information on arbiter