PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 306

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Arithmetic shift left
SYNTAX
FUNCTION
DESCRIPTION
and rdest is set to rsrc1 arithmetically shifted left by this amount. If the rsrc2<31:5> value is not zero, then take this as
a shift by 32 or more bits. Zeros are shifted into the LSBs of rdest while the MSBs shifted out of rsrc1 are lost.
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
EXAMPLES
r60 = 0x20, r30 = 3
r10 = 0, r60 = 0x20, r30 = 3
r20 = 1, r60 = 0x20, r30 = 3
r70 = 0xfffffffc, r40 = 2
r80 = 0xe, r50 = 0xfffffffe
r30 = 0x7008000f, r60 = 0x20
r30 = 0x8008000f, r45 = 0x80000000
r30 = 0x8008000f, r45 = 0x23
As shown below, the
The
[ IF rguard ] asl rsrc1 rsrc2 → rdest
if rguard then {
}
rsrc1
n ← rsrc2<4:0>
rdest<31:n> ← rsrc1<31–n:0>
rdest<n–1:0> ← 0
if rsrc2<31:5> != 0 {
}
31
rdest <- 0
asl
Initial Values
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
Intermediate result
(example: n = 3)
asl
operation takes two arguments, rsrc1 and rsrc2. Rsrc2 specify an unsigned shift amount,
rdest
asl r60 r30 → r90
IF r10 asl r60 r30 → r100
IF r20 asl r60 r30 → r110
asl r70 r40 → r120
asl r80 r50 → r125
asl r30 r60 → r111
asl r30 r45 → r100
asl r30 r45 → r100
31
32 bits from rsrc1
Operation
0
Left shifter
PRELIMINARY SPECIFICATION
rsrc2
31
PNX1300/01/02/11 DSPCPU Operations
r90 ← 0x100
no change, since guard is false
r110 ← 0x100
r120 ← 0xfffffff0
r125 ← 0x00000000 (shift by more than 32)
r111 ← 0x00000000
r100 ← 0x00000000
r100 ← 0x00000000
3
0
0
0
0
0
0
0
asli asr asri lsl lsli lsr
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
lsri rol roli
Result
ATTRIBUTES
SEE ALSO
rsrc2
shifter
1, 2
No
19
—
0
2
1
asl
A-8