PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 190

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
Table 12-15. Glueless interface limits for address/
clocks
• Signal traces between PNX1300 and the memory
• The clock-signal trace(s) must be as short as possi-
• Address and control-signal traces should also be
• Data-signal traces should also be short, but their
• Connections to several loads must follow a “T” con-
12.15.2 Specific Guidelines
• The maximum length for a signal trace should be
• The maximum capacitive load is 30 pF per trace,
• The signal traces on the PNX1300 circuit board must
• At most one SDRAM device may be connected to
12-8
Figure 12-4. Conceptual board layout.
capacitance. Close proximity is especially important
for a 183-MHz memory system.
chips must be matched in length as closely as possi-
ble to minimize signal skew.
ble.
short, but their length is less critical than the clock’s.
length is less critical than the clock’s, especially if
only one or two ranks are connected.
nection scheme in order to limit the reflections.
10cm. For 183-MHz operation, signal trace length
must not be longer than 7cm.
including loads.
be designed as 50-ohm transmission lines.
each MM_CLK signal at 183 MHz.
Memory Chips
2
4
8
DSPCPU
PNX1300
Peripherals
On-Chip
PRELIMINARY SPECIFICATION
Highway
Data
PNX1300
Maximum Clock Frequency
Interface
Memory
183 MHz
166 MHz
133 MHz
RAS#, CAS#, WE#
Clock Enables,
Data[31:0]
Address,
Clock
33 Ω
12.15.3 Termination
No termination is required for address, data, and control
signals. Address and control signals are driven only by
PNX1300; the output impedance of the drivers is suffi-
ciently matched to prevent excessive ringing. PNX1300
design assumes that when driving data lines, the output
drivers of SDRAM chips are also sufficiently impedance
matched.
Series termination of the clock outputs with a 33-ohm re-
sistor is advised.
12.16 TIMING BUDGET
The glueless interface of the PNX1300 main-memory in-
terface makes the memory system simple and straight-
forward from one point of view, but to ensure reliable op-
eration at high clock rates, system designers must follow
the board design guidelines (see
Board
SDRAM devices must meet the critical specifications list-
ed in
MHz (T
Table 12-16. Critical 143-MHz SDRAM parameters
For a 166 MHz operation, SDRAM devices must meet
the critical specifications listed in
Max. output delay
Min. output hold time
Max. input setup time
Max. input hold time
Table 12-16
Design”).
cycle
Timing Parameter
= 7 ns) memory system.
to ensure reliable operation of an 143-
t
t
t
t
AC
OH
IS
IH
Philips Semiconductors
Section 12.15, “Circuit
Table 12-17
SDRAM
Device
SDRAM
Device
6.4 ns
2.0 ns
2.0 ns
1.0 ns
Value
to ensure