PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 271

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
• Five JTAG instructions
• In the capture-IR state of the TAP controller, the least
Race Conditions
Since the JTAG data registers live in MMIO space and
are accessible by both the TriMedia processor and the
JTAG controller at the same time, race conditions must
not exist either in hardware or in software. The following
communication protocol uses a handshake mechanism
to avoid software race conditions.
18.3.2
The following describes the handshake mechanism for
transferring data via JTAG.
• Transfer from debug front-end to debug monitor
JTAG_IFULL_IN
JTAG_CTRL.ifull and JTAG_DATA_IN in series.
Likewise, the virtual register JTAG_OFULL_OUT
connects JTAG_CTRL.ofull and JTAG_DATA_OUT
in series.
The reason for the virtual registers is to shorten the
time
JTAG_DATA_OUT registers. Without virtual regis-
ters, we must scan in an instruction to select
JTAG_DATA_IN, scan in data, scan an instruction to
select JTAG_CTRL register and finally scan in the
control register. With virtual register, we can scan in
an instruction to select JTAG_IFULL_IN and then
scan in both control and data bits. Similar savings
can be achieved for scan out using virtual registers.
• 5 instructions, SEL_DATA_IN, SEL_DATA_OUT,
• An instruction RESET for resetting the TriMedia
2 significant bits (bits 0 and 1) of the shift register
stage must be loaded with the ‘01’ as required in the
standard. The standard allows the remaining bits of
the IR shift stage to be loaded with design specific
data. The bits 2, 3 and 4 of the IR shift stage are
loaded with bits 0, 1 and 2 of the JTAG_CTRL regis-
ter. This means that shifting in any instruction allows
the 3 least significant bits of the JTAG_CTRL register
to be inspected. This reduces the polling overhead
for data transfer.
The debugger front-end running on a host transfers
data to a debug monitor via JTAG_DATA_IN regis-
ter. It must poll JTAG_CTRL.ifull bit to check if
JTAG_DATA_IN register can be written to. If the
JTAG_CTRL.ifull bit is clear, the front-end may scan
data into JTAG_DATA_IFULL_IN register. Note that
data and control bits may be shifted in with
SEL_IFULL_IN instruction and the bit shifted into
SEL_IFULL_IN,
SEL_JTAG_CTRL, for selecting the registers to
be connected between TDI and TDO for serial
input/output.
processor to power on state.
for
JTAG Communication Protocol
scanning
connects
the
SEL_OFULL_OUT,
JTAG_DATA_IN
the
registers
and
and
• Transfer from monitor to front-end
• Controller States
18.3.3
Scanning in a 5-bit instruction will take 12 TCK cycles
from the Run-Test/Idle state: 4 cycles to reach Shift-IR
state, 5 cycles for actual shifting in, 1 cycle to exit1-IR
state, 1 cycle to Update-IR state, and 1 cycle back to
Run-Test/Idle state. Likewise, scanning in a 32 bit data
register will take 38 TCK cycles and transferring an 8-bit
JTAG_CTRL data register will take 14 TCK cycles from
Idle state. However, if a data transfer follows instruction
transfer, then the transition to DR scan stage can be
done without going through Idle state, saving 1 cycle.
18.3.3.1
Poll control register to check if input buffer is empty. Scan
in data when it is empty and set the ifull control bit to ‘1’
triggering an interrupt. Note that scanning in any instruc-
tion automatically scans out the 3 least significant bits
(including ifull and ofull bits) of the JTAG_CTRL register.
Table 18-3. Transfer of Data in via JTAG
PRELIMINARY SPECIFICATION
IR shift in SEL_IFULL_IN instruction
While JTAG_CTRL.ifull = 1, scan in
SEL_IFULL_IN instruction
DR scan 33 bits of register JTAG_IFULL_IN
TOTAL
JTAG_CTRL.ifull register must be ‘1’. This action
triggers an interrupt. The debug monitor must copy
the data from JTAG_DATA_IN register into its private
area when servicing the interrupt and then clear
JTAG_CTRL.ifull bit thus allowing JTAG interface
module to write to JTAG_DATA_IN register the next
piece of data.
The monitor running on TriMedia must check if
JTAG_CTRL.ofull is clear and if so, it can write data
to JTAG_DATA_OUT. After that, the monitor must
set the JTAG_CTRL.ofull bit. The debugger front-end
polls the JTAG_CTRL.ofull bit. When that bit is set, it
can scan out JTAG_DATA_OUT register and clear
JTAG_CTRL.ofull bit. Since JTAG_DATA_OUT is
read-only via JTAG, the update action at the end of
scan out has no effect on JTAG_DATA_OUT. The
JTAG_CTRL.ofull bit, however, must be cleared by
shifting in the value ‘1’.
In the power-on reset state, JTAG_CTRL.ifull and
JTAG_CTRL.ofull must be cleared by the JTAG con-
troller.
Example Data Transfer Via JTAG
Transferring data to TriMedia via
JTAG
Action
JTAG Functional Specification
TCK cycles
Number of
61+ cycles
11+
38
12
18-5