PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 206

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
instructions. The byte count must be a multiple of four.
Note that the bytes are stored in the EEPROM in a byte
swapped order per group of 4 compared to SDRAM, as
detailed in
After the entire DSPCPU bootstrap program is loaded
into SDRAM at DRAM_BASE, the system boot logic re-
leases the DSPCPU from the reset state. At this point,
the DSPCPU begins executing the bootstrap program
starting at DRAM_BASE and PNX1300 is fully operation-
al. At the same time, the boot logic releases the I
face.
13.3
For a host-assisted bootstrap, the complete bootstrap
process consists of three distinct stages, but the system
boot hardware performs only the first stage. The other
two stages are the responsibility of the host system.
13.3.1
In the first stage, the PNX1300 hardware must be initial-
ized enough to allow the host system to query and ma-
nipulate PNX1300 resources. The system boot hard-
ware, using the procedure described above in
13.2.1, “Boot Procedure Common to Both Autonomous
and Host-Assisted Bootstrap,”
ID,
PLL_RATIOS registers, waits for the PLLs to lock, en-
ables the internal highway and MMI, but leaves the
DSPCPU in the reset state. After this minimal initializa-
tion, the host system can finish the bootstrap process.
At the completion of stage 1, the PNX1300 hardware is
ready to respond to PCI configuration space accesses,
and the boot block has released the I
13.3.2
Stage 2 is carried out either by the host-system PCI
BIOS or by a combination of the BIOS and the host op-
erating system (e.g., Windows 95). During this stage, the
host system configures all PCI-bus clients.
The PCI-bus configuration consists of querying the bus
clients to determine the following:
• The number of PCI base-address registers imple-
• The size of each aperture associated with the base-
Using this information, the host system relocates each
address aperture to eliminate overlaps in the PCI ad-
13-6
mented by each client. For PNX1300, the number of
PCI
(MMIO_BASE and DRAM_BASE).
address registers. For PNX1300, the size of the
MMIO aperture is always 2 MB. The size of the
SDRAM aperture can range from 1 MB to 64 MB,
and the size must be a power of two (seven distinct
sizes).
Subsystem
HOST-ASSISTED BOOT
DESCRIPTION
base-address
Stage 1: PNX1300 System Boot
Hardware
Stage 2: Host-System PCI
Configuration
Table
13-5.
Vendor
PRELIMINARY SPECIFICATION
registers
ID,
initializes the Subsystem
MM_CONFIG,
2
C interface.
is
always
2
Section
C inter-
and
two
dress space. The host system accomplishes the reloca-
tion by considering each aperture’s size and then writing
an appropriate starting address to each base-address
register. For PNX1300, the base addresses of the MMIO
and SDRAM apertures must be relocated in this way.
Note that in the case of autonomous boot, this relocation
is done statically by the system boot hardware when it
simply
DRAM_BASE from the serial EEPROM into these regis-
ters.
The steps of the PCI protocol for determining the size of
an address aperture are as follows (see
“Base Address Registers,”
sion):
• The host writes a 32-bit word of all ‘1’s (0xffffffff) to
• The host reads the base-address register immedi-
• This left-aligned field of ‘1’s effectively specifies the
As an example, consider the case of the MMIO aperture.
The host will perform the following steps during stage 2
of the bootstrap process:
• Write 0xffffffff to MMIO_BASE.
• Read from MMIO_BASE, which returns the value
• Write a new value to MMIO_BASE with the top 11
At the completion of stage 2, the PNX1300 hardware is
ready to respond to host configuration space accesses,
host MMIO accesses and host SDRAM aperture access-
es. The DSPCPU is still in RESET state.
13.3.3
During the final stage of the bootstrap process, the
PNX1300 software driver executing on the host system
will write to SDRAM a program for the DSPCPU, and ini-
tialize any MMIO registers. When the initial program load
is complete, the driver releases the DSPCPU from its re-
set state by a write to the BIU_CTL register with the CR
bit set. See
DSPCPU and host both running, the PNX1300 bootstrap
process is complete.
the base-address register.
ately after the write. The value returned will have ‘0’s
in all don’t-care bits and ‘1’s in all required address
bits. The required address bits form a left-aligned
(i.e., starting at the most-significant bit) contiguous
field of ‘1’s.
size of the address aperture by indicating the bits of
the base-address register that are significant for relo-
cation. That is, an address aperture of size 2
only begin on a 2
0xffe00000. The host sees that this value has an 11-
bit left-aligned field of ‘1’s, which indicates that the
aperture can only be relocated on 2-MB boundaries;
thus, the aperture size is 2 MB.
bits set to relocate the MMIO aperture to a 2-MB
region of PCI address space that does not conflict
with other PCI address apertures.
copies
Stage 3: PNX1300 Driver Executing on
the Host
Chapter 11, “PCI Interface.”
the
n
-byte-aligned boundary.
values
Philips Semiconductors
for a more complete discus-
of
MMIO_BASE
Section 11.5.11,
Now, with the
n
and
can