PEF2054NV21XK Infineon Technologies, PEF2054NV21XK Datasheet - Page 124

• Manufacturer Part Number: PEF2054NV21XK
• Manufacturer: Infineon Technologies

Specifications of PEF2054NV21XK

• Lead Free Status / Rohs Status: Compliant

From this it follows that:
CTAR:TSN6 … 0 = TSN + 2 = 0 + 2 = 2
Examples
1) In CFI mode 0, with a frame consisting of 32 time slots, the following timing
Figure 44
Timing Signals for CFI Bit Shift Example 1
The framing signal source PFS shall mark CFI time slot 31, bit 1 in downstream direction
and CFI time slot 0, bit 5 in upstream direction. The data shall be transmitted and
sampled with the falling CRCL edge. The timing of the FSC and DCL output signals shall
be as shown in figure 44. The PFS signal is sampled with the rising PDC edge.
The following CFI register values result:
Since PFS marks the downstream bit 1, the CBSR:CDS bits must be set to “000”,
according to table 18.
If the CBSR:CDS bits are set to “000”, PFS marks the time slot TSN – 1, according to
table 18.
PFS shall mark CFI time slot 31, i.e. TSN – 1 = 31, or
TSN = 31 + 1 = (32)
The upstream CFI frame shall be shifted by 4 bits to the left (TS31, bit 1 + 4 bits yields
in TS0, bit 5).
Semiconductor Group
PFS
PDC/
CRCL
DD#
DU#
FSC
DCL
relationship between the framing signal source PFS and the data signals is required:
TS31, Bit 2
TS0,
0
Bit 6
mod 32
1
= 0
TS31, Bit 1
TS0, Bit 5
TS31, Bit 0
TS0,
Bit 4
D
= 0000010
124
TS0,
TS0,
Bit 7
Bit 3
B
; i.e. CTAR = 02
TS0,
TS0,
Bit 6
Bit 2
Application Hints
H
Condition:
CMD1
PMOD PSM = 1
CFI Mode 0
CMD2 CXF = 1
CMD2
CMD2
CMD2 COC = 0
:
:
:
:
:
:
CSM
PEB 2055
CRR
FC2
PEF 2055
...0
=
=
1
0
ITT08059
=
011