PEF2054NV21XK Infineon Technologies, PEF2054NV21XK Datasheet - Page 225

• Manufacturer Part Number: PEF2054NV21XK
• Manufacturer: Infineon Technologies

Specifications of PEF2054NV21XK

• Lead Free Status / Rohs Status: Compliant

PICM:
Table 34
PCM Mode
2
0
the following information from the EPIC:
Interrupt!
R: ISTA
R: PICM
In order to determine the line actually at fault (RxD0 or RxD1) the system must send a
known pattern in one of the time slots and compare the actually received value with that
known pattern.
PCM Input Comparison Mismatch
The contents of the PICM register is only valid after an ISTA:PIM interrupt!
The PICM register must be read after an ISTA:PIM interrupt in order to enable a new
PIM interrupt generation.
IPN:
TSN6 … 0:
1
Example
In PCM mode 1, the logical PCM port 0 is connected to two physical PCM transmission
links. The comparison function for RxD0/RxD1 is enabled via PMOD:AIC0 = 1. Suddenly
a bit error occurs at one of the receive lines in time slot 13, bit 2. The P would then get
Semiconductor Group
bit 7
= 04
= 13
IPN
Time Slot Identification
[TSN6 … 0 + 8]
[TSN6 … 1 + 4]
[TSN6 … 2 + 2]
H
H
Input Pair Number; this bit indicates the pair of input lines where a
mismatch occurred. A logical 0 indicates a mismatch between lines
RxD0 and RxD1, a logical 1 between lines RxD2 and RxD3.
Time slot Number 6 … 0; these bits specify the time slot number and
the bit positions that generated the ISTA:PIM interrupt according to
the table below. TPF denotes the number of time slots per PCM frame
TSN6
; PIM interrupt
; IPN = 0, TSN6 … 1 = 9, TSN0 = 1
TSN5
mod TPF
mod TPF
mod TPF
TSN4
225
read
TSN3
Bit Identification
TSN0 = 1 : bits 3 … 0
TSN0 = 0 : bits 7 … 4
TSN1 … 0 = 11 : bits 1 … 0
TSN1 … 0 = 10 : bits 3 … 2
TSN1 … 0 = 01 : bits 5 … 4
TSN1 … 0 = 00 : bits 7 … 6
reset value:
TSN2
Application Hints
TSN1
undefined
PEB 2055
PEF 2055
bit 0
TSN0