PEF2054NV21XK Infineon Technologies, PEF2054NV21XK Datasheet - Page 68

• Manufacturer Part Number: PEF2054NV21XK
• Manufacturer: Infineon Technologies

Specifications of PEF2054NV21XK

• Lead Free Status / Rohs Status: Compliant

Semiconductor Group
4.2.4.3 Synchronous Transfer Receive Address Register A (SARA)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: xx
The SARA register specifies for synchronous transfer channel A from which input
interface, port and time slot the serial data is extracted. This data can then be read from
the STDA register.
ISRA
MTRA6..0
bit 7
ISRA
MTRA6
Interface Select Receive for channel A.
0… selects the PCM interface as the input interface for synchronous
1… selects the CFI interface as the input interface for synchronous
number at the interface selected by ISRA according to tables 3 and 4:
MTRA6..0 = MA6..0.
P Transfer Receive Address for channel A; selects the port and time slot
H
channel A.
channel A.
MTRA5
MTRA4
68
MTRA3
read/write
read/write
Detailed Register Description
MTRA2
OMDR:RBS = 0
address: 0A
address: 5
MTRA1
PEB 2055
PEF 2055
H
bit 0
H
MTRA0