PEF2054NV21XK Infineon Technologies, PEF2054NV21XK Datasheet - Page 97

• Manufacturer Part Number: PEF2054NV21XK
• Manufacturer: Infineon Technologies

Specifications of PEF2054NV21XK

• Lead Free Status / Rohs Status: Compliant

The PCM interface shall be clocked with a PDC having the same frequency as the data
rate i.e. 2.048 MHz. Since the rising edge of PFS occurs at the same time as the rising
edge of PDC, it is recommended to select the falling PDC edge for sampling the PFS
signal (PMOD:PSM0 = 0). In this case the 1st bit of internal framing structure (according
to figure 26) will represent time slot 0, bit 6 (2nd bit) of the external frame (according to
figure 24). The values to be programmed to the POFD, POFD and PCSR can now be
determined as follows:
With BND = BNU = 2 and BPF = 256:
POFD = OFD9 … 2 = (BND – 17 + BPF)
POFU = OFU9 … 2 = (BNU + 23)
With URE = 1 and DRE = 0:
PCSR = 01
2) In PCM mode 1, with a frame consisting of 48 time slots, the following timing
Figure 27
Timing for PCM Frame Offset of Example 2
Semiconductor Group
PFS
PDC
TxD#
Required
Time-Slot/Bit
Offset in
Upstream
Direction
Required
Time-Slot/Bit
Offset in
Downstream
Direction
RxD#
relationship between the framing signal and the data signals is required:
H
Bit 3
381
Bit 7
1
Bit 2
382
0
Bit 6
2
1
Time-Slot 47
Start of Internal Frame
Bit 1
BNU
383
mod BPF
Bit 5
BND
3
= (2 + 23)
mod BPF
Time-Slot 0
Bit 0
97
384
= (2 – 17 + 256)
Bit 4
4
mod 256
Bit 7
1
= 25
Bit 3
5
Time-Slot 0
D
= 19
Bit 6
mod 256
2
H
Bit 2
Application Hints
6
= 241
Bit 5
3
PMOD
PCSR URE = 1
PCSR :
D
PEB 2055
PEF 2055
= F1
:
:
DRE
PSM
ITT08042
H
=
=
1
1