PEF2054NV21XK Infineon Technologies, PEF2054NV21XK Datasheet - Page 71

• Manufacturer Part Number: PEF2054NV21XK
• Manufacturer: Infineon Technologies

Specifications of PEF2054NV21XK

• Lead Free Status / Rohs Status: Compliant

Access in multiplexed P-interface mode:
This register is only used in IOM-2 applications (active handshake protocol) in order to
identify active monitor channels when the “Search for active monitor channels”
command (CMDR:MFSO) has been executed.
SO
SAD5..0
CTA2..0
CTB2..0
4.2.5
4.2.5.1 MF-Channel Active Indication Register (MFAIR)
Access in demultiplexed P-interface mode:
Reset value: 00
Semiconductor Group
bit 7
0
Monitor/Feature Control Registers
Channel Type A (B); these bits determine the bandwidth of the channel and
the position of the relevant bits in the time slot according to the table below.
CT#2
0
0
0
0
1
1
1
1
Note:Note that if a CFI time slot is selected as receive or transmit time slot of
MF Channel Search On.
0…the search is completed.
1…the EPIC is still busy looking for an active channel.
Subscriber Address 5..0; after an ISTA:MAC interrupt these bits point to the
port and time slot where an active channel has been found. The coding is
identical to MFSAR:SAD5..SAD0.
SO
H
the synchronous transfer, the 64-kbit/s bandwidth must be selected
(CT#2..CT#0 = 001).
CT#1
0
0
1
1
0
0
1
1
SAD5
CT#0
0
1
0
1
0
1
0
1
SAD4
Bandwidth
not allowed
64 kbit/s
32 kbit/s
32 kbit/s
16 kbit/s
16 kbit/s
16 kbit/s
16 kbit/s
71
SAD3
read
read
Detailed Register Description
SAD2
–
bits 7..0
bits 3..0
bits 7..4
bits 1..0
bits 3..2
bits 5..4
bits 7..6
Transferred Bits
address: A
OMDR:RBS = 0
address: 14
SAD1
PEB 2055
PEF 2055
H
bit 0
H
SAD0