EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 131

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

Chapter 4: DC and Switching Characteristics
Operating Conditions
Table 4–7. Arria GX Transceiver Block AC Specification
© December 2009 Altera Corporation
Deterministic jitter at 3.125 Gbps
XAUI Receiver Jitter Tolerance
Total jitter
Deterministic jitter
Peak-to-peak jitter
Peak-to-peak jitter
Peak-to-peak jitter
PCI Express (PIPE) Transmitter Jitter Generation
Total Transmitter Jitter Generation
PCI Express (PIPE) Receiver Jitter Tolerance
Total Receiver Jitter Tolerance
Gigabit Ethernet (GIGE) Transmitter Jitter Generation
Total Transmitter Jitter Generation (TJ)
Deterministic Transmitter Jitter
Generation (DJ)
Gigabit Ethernet (GIGE) Receiver Jitter Tolerance
Total Jitter Tolerance
Deterministic Jitter Tolerance
Serial RapidIO (1.25 Gbps, 2.5 Gbps, and 3.125 Gbps) Transmitter Jitter Generation
Total Transmitter Jitter Generation (TJ)
Deterministic Transmitter Jitter
Generation (DJ)
Description
(4)
REFCLK
Pattern = CJPAT
V
No Pre-emphasis
Pattern = CJPAT
No Equalization
DC Gain = 3 dB
Pattern = CJPAT
No Equalization
DC Gain = 3 dB
Jitter frequency = 22.1 KHz
Jitter frequency = 1.875 MHz
Jitter frequency = 20 MHz
Compliance Pattern; V
Pre-emphasis = 49%
Compliance Pattern;
DC Gain = 3 db
CRPAT: V
Pre-emphasis = 0%
CRPAT; V
Pre-emphasis = 0%
CJPAT Compliance Pattern;
DC Gain = 0 dB
CJPAT Compliance Pattern;
DC Gain = 0 dB
CJPAT Compliance Pattern;
V
Pre-emphasis = 0%
CJPAT Compliance Pattern;
V
Pre-emphasis = 0%
OD
OD
OD
(5)
= 1200 mV
= 800 mV;
= 800 mV;
(5)
= 156.25 MHz
OD
OD
= 800 mV;
= 800 mV;
(7)
(Note
1), (2),
Condition
OD
= 800 mV;
(3)
(Part 2 of 4)
(6)
Arria GX Device Handbook, Volume 1
–6 Speed Grade
Commercial &
Industrial
< 0.279
> 0.65
> 0.37
< 0.25
< 0.14
> 0.66
< 0.35
< 0.17
> 8.5
> 0.1
> 0.1
> 0.6
> 0.4
0.17
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
Units
UI
UI
UI
UI
UI
UI
4–9