EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 28

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

2–22
Reverse Serial Pre-CDR Loopback
Figure 2–20. Arria GX Block in Reverse Serial Pre-CDR Loopback Mode
Figure 2–21. PCI Express (PIPE) Reverse Parallel Loopback
Arria GX Device Handbook, Volume 1
FPGA
Logic
Array
Interface
PIPE
Transmitter Digital Logic
Receiver Digital Logic
Incremental
Incremental
Generator
RX Phase
Compen-
Verify
BIST
BIST
sation
FIFO
Compensation
TX Phase
FIFO
Reverse serial pre-CDR loopback mode uses the analog portion of the transceiver. An
external source (pattern generator or transceiver) generates the source data. The
high-speed serial source data arrives at the high-speed differential receiver input
buffer, loops back before the CRU unit, and is transmitted though the high-speed
differential transmitter output buffer. It is for test or verification use only to verify the
signal being received after the gain and equalization improvements of the input
buffer. The signal at the output is not exactly what is received because the signal goes
through the output buffer and the V
Pre-emphasis settings have no effect.
Figure 2–20
PCI Express (PIPE) Reverse Parallel Loopback
Figure 2–21
reverse parallel loopback configuration is compliant with the PCI Express (PIPE)
specification and is available only on PCI Express (PIPE) mode.
RX Phase
Compe-
nsation
FIFO
Serializer
TX Phase
Compe-
nsation
Byte
FIFO
shows the data path for PCI Express (PIPE) reverse parallel loopback. The
Serializer
shows the Arria GX block in reverse serial pre-CDR loopback mode.
Serializer
20
serializer
Byte
Byte
De-
Byte
De-
Encoder
8B/10B
Encoder
Decoder
8B/10B
8B/10B
Decoder
8B/10B
Generator
PRBS
BIST
Parallel Loopback
O D
PIPE Reverse
Match
FIFO
Rate
is changed to the V
Match
Rate
FIFO
Transmitter PCS
Receiver PCS
Deskew
FIFO
Aligner
Word
PRBS
Verify
BIST
Aligner
Word
© December 2009 Altera Corporation
OD
Receiver PMA
Serializer
setting level.
Chapter 2: Arria GX Architecture
De-
Transmitter PMA
Analog Receiver and
Transmitter Logic
Serializer
serializer
Serializer
De-
Recovery
Clock
Unit
Reverse
Serial
Pre-CDR
Loopback
Recovery
Clock
Unit
Transceivers