EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 162

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

4–40
Table 4–51. EP1AGX20 Column Pins Output Timing Parameters (Part 4 of 4)
Arria GX Device Handbook, Volume 1
3.3-V PCI
3.3-V PCI-X
LVDS
I/O Standard
Strength
Drive
—
—
—
Table 4–52
should be added to GCLK values. These adder values are used to determine I/O
timing when the I/O pin is driven using the regional clock. This applies for all I/O
standards supported by Arria GX with general purpose I/O pins.
Table 4–52
devices.
Table 4–52. EP1AGX20 Row Pin Delay Adders for Regional Clock
Table 4–53
devices.
Table 4–53. EP1AGX20 Column Pin Delay Adders for Regional Clock
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
RCLK input adder
RCLK PLL input
adder
RCLK output
adder
RCLK PLL output
adder
Parameter
Parameter
GCLK PLL
GCLK PLL
GCLK PLL
GCLK
GCLK
GCLK
Clock
through
describes row pin delay adders when using the regional clock in Arria GX
lists column pin delay adders when using the regional clock in Arria GX
Table 4–53
Parameter
Industrial
–0.012
–0.081
0.081
1.11
t
t
t
t
t
t
CO
CO
CO
CO
CO
CO
Industrial
–0.117
–0.011
0.117
0.011
Fast Corner
list EP1AGX20 regional clock (RCLK) adder values that
Fast Corner
Industrial
2.755
1.313
2.755
1.313
3.621
2.190
Commercial
–0.012
–0.081
0.081
Fast Corner
Commercial
1.11
–0.117
–0.011
0.117
0.011
Commercial
2.755
1.313
2.755
1.313
3.621
2.190
Chapter 4: DC and Switching Characteristics
–6 Speed Grade
–6 Speed Grade
–0.008
–0.224
© December 2009 Altera Corporation
0.223
2.658
–0.273
–0.019
0.273
0.019
–6 Speed
Grade
5.791
2.685
5.791
2.685
6.969
3.880
Typical Design Performance
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns