EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 89

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

Chapter 2: Arria GX Architecture
I/O Structure
Figure 2–68. Row I/O Block Connection to the Interconnect
Note to
(1) The 32 data and control signals consist of eight data out lines: four lines each for DDR applications io_dataouta[3..0] and
© December 2009 Altera Corporation
io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables io_ce_in[3..0], four output clock enables
io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous clear and preset signals io_aclr/apreset[3..0], and four
synchronous clear and preset signals io_sclr/spreset[3..0].
Figure
2–68:
Interconnect
LAB Local
Interconnects
to Adjacent LAB
R4 & R24
Interconnect
Figure 2–68
Direct Link
LAB
shows how a row I/O block connects to the logic array.
io_dataina[3..0]
io_datainb[3..0]
C4 Interconnect
to Adjacent LAB
Interconnect
Direct Link
I/O Block Local
Interconnect
io_clk[7:0]
32
Horizontal
I/O Block
up to Four IOEs
Block Contains
Horizontal I/O
Arria GX Device Handbook, Volume 1
32 Data & Control
Signals from
Logic Array (1)
2–83