EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 81

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

Chapter 2: Arria GX Architecture
PLLs and Clock Networks
Figure 2–63. Global and Regional Clock Connections from Corner Clock Pins and Fast PLL Outputs
Note to
(1) The GCLK or RCLK in a fast PLL's quadrant can drive the fast PLL input. A dedicated clock input pin or other PLL must drive the global or regional
Table 2–19. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs (Part 1 of 2)
© December 2009 Altera Corporation
Clock Pins
CLK0p
CLK1p
CLK2p
CLK3p
Drivers from Internal Logic
GCLKDRV0
GCLKDRV1
GCLKDRV2
GCLKDRV3
RCLKDRV0
RCLKDRV1
RCLKDRV2
RCLKDRV3
RCLKDRV4
RCLKDRV5
RCLKDRV6
Clock Network Connectivity
Left Side Global & Regional
source. The source cannot be driven by internally generated logic before driving the fast PLL.
Figure
2–63:
PLL 7
PLL 8
Fast
Fast
v
v
v
v
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C0
C1
C2
C3
C0
C1
C2
C3
v
v
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v
v
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RCLK0
RCLK4
v
v
v
v
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RCLK1
RCLK5
RCLK2
RCLK6
v
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RCLK3
RCLK7
v
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GCLK0
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GCLK1
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GCLK2
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GCLK3
v
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v
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Arria GX Device Handbook, Volume 1
v
v
v
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(Note 1)
v
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v
v
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