EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 49

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

Chapter 2: Arria GX Architecture
Adaptive Logic Modules
Figure 2–38. Register Chain within a LAB
Note to
(1) The combinational or adder logic can be used to implement an unrelated, unregistered function.
Clear and Preset Logic Control
© December 2009 Altera Corporation
Figure 2–38
:
LAB-wide signals control the logic for the register ’s clear and load/preset signals. The
ALM directly supports an asynchronous clear and preset function. The register preset
is achieved through the asynchronous load of a logic high. The direct asynchronous
preset does not require a NOT gate push-back technique. Arria GX devices support
simultaneous asynchronous load/preset and clear signals. An asynchronous clear
signal takes precedence if both signals are asserted simultaneously. Each LAB
supports up to two clears and one load/preset signal.
Combinational
Combinational
Logic
Logic
(Note 1)
adder0
adder1
adder0
adder1
reg_chain_out
reg_chain_in
D
D
D
D
reg0
reg1
reg0
reg1
From Previous ALM
Within The LAB
To Next ALM
within the LAB
Q
Q
Q
Q
To general or
To general or
To general or
To general or
To general or
To general or
To general or
To general or
Arria GX Device Handbook, Volume 1
local routing
local routing
local routing
local routing
local routing
local routing
local routing
local routing
2–43