EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 94

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

2–88
Figure 2–73. Arria GX IOE in DDR Input I/O Configuration
Notes to
(1) All input signals to the IOE can be inverted at the IOE.
(2) This signal connection is only allowed on dedicated DQ function pins.
(3) This signal is for dedicated DQS function pins only.
(4) The optional PCI clamp is only available on column I/O pins.
Figure 2–74. Input Timing Diagram in DDR Mode
Arria GX Device Handbook, Volume 1
Column, Row,
Figure
Interconnect
or Local
2–73:
ioe_clk[7..0]
Input To
Logic Array
DQS Local
Bus (2)
Data at
input pin
CLK
sclr/spreset
clkin
ce_in
aclr/apreset
Chip-Wide Reset
B0
A0
B1
A0
B0
A1
B2
A1
B1
Input Register
Input Register
CLRN/PRN
D
ENA
CLRN/PRN
D
ENA
Input RegisterDelay
A2
(Note 1)
I
nput Pin to
B3
A2
B2
Q
Q
A3
D
ENA
CLRN/PRN
B4
A3
B3
To DQS Logic
Latch
Block (3)
Q
VCCIO
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
VCCIO
PCI Clamp (4)
Bus-Hold
Termination
Circuit
On-Chip
Programmable
Pull-Up
Resistor
I/O Structure