MC68306EH16B Freescale Semiconductor, MC68306EH16B Datasheet - Page 131

• Manufacturer Part Number: MC68306EH16B
• Description: IC MPU INTEGRATED 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68306EH16B

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Cpu Speed: 16.7MHz
• No. Of Timers: 1
• Embedded Interface Type: UART
• Digital Ic Case Style: PQFP
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

FE—Framing Error
PE—Parity Error
OE—Overrun Error
TxEMP—Transmitter Empty
TxRDY—Transmitter Ready
FFULL—FIFO Full
MOTOROLA
This bit is duplicated in the DUISR; bit 0 for channel A and bit 4 for channel B.
1 = A stop bit was not detected when the corresponding data character in the FIFO
0 = No framing error has occurred.
1 = When the with parity or force parity mode is programmed in the DUMR1, the
0 = No parity error has occurred.
1 = One or more characters in the received data stream have been lost. This bit is
0 = No overrun has occurred.
1 = The channel transmitter has underrun (both the transmitter holding register and
0 = The transmitter buffer is not empty. Either a character is currently being shifted
1 = The transmitter holding register is empty and ready to be loaded with a character.
0 = The transmitter holding register was loaded by the CPU, or the transmitter is
1 = A character has been received in channel B and is waiting in the receiver buffer
0 = The FIFO is not full, but may contain up to two unread characters.
was received. The stop-bit check is made in the middle of the first stop-bit
position. The bit is valid only when the RxRDY bit is set.
corresponding character in the FIFO was received with incorrect parity. When the
multidrop mode is programmed, this bit stores the received A/D bit. This bit is
valid only when the RxRDY bit is set.
set upon receipt of a new character when the FIFO is full and a character is
already in the shift register waiting for an empty FIFO position. When this occurs,
the character in the receiver shift register and its break detect, framing error
status, and parity error, if any, are lost. This bit is cleared by the reset error status
command in the DUCR.
transmitter shift registers are empty). This bit is set after transmission of the last
stop bit of a character if there are no characters in the transmitter holding register
awaiting transmission.
out, or the transmitter is disabled. The transmitter is enabled/disabled by
programming the TCx bits in the DUCR.
This bit is set when the character is transferred to the transmitter shift register.
This bit is also set when the transmitter is first enabled. Characters loaded into
the transmitter holding register while the transmitter is disabled are not
transmitted.
disabled.
FIFO.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68306 USER'S MANUAL
Go to: www.freescale.com
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