MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 101

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

Internal Bus Monitor
Double Bus Fault Monitor
Spurious Interrupt Monitor
Software Watchdog
Periodic Interrupt Timer
Figure 4-2 shows a block diagram of the system configuration and protection function.
4-4
The SIM40 provides an internal bus monitor to monitor the DSACK response time for
all internal bus accesses. An option allows the monitoring of external bus accesses. For
external bus accesses, four selectable response times are provided to allow for
variations in response speed of memory and peripherals used in the system. A bus
error signal is asserted internally if the DSACK response limit is exceeded. BERR is
not asserted externally. This monitor can be disabled for external bus cycles only.
The double bus fault monitor causes a reset to occur if the internal HALT is asserted by
the CPU32, indicating a double bus fault. A double bus fault results when a bus or
address error occurs during the exception processing sequence for a previous bus or
address error, a reset, or while the CPU32 is loading information from a bus error stack
frame during an RTE instruction. This function can be disabled. See Section 3 Bus
Operation for more information.
If no interrupt arbitration occurs during an interrupt acknowledge (IACK) cycle, the bus
error signal is asserted internally. This function cannot be disabled.
The software watchdog asserts reset or a level 7 interrupt (as selected by the system
protection and control register) if the software fails to service the software watchdog for
a designated period of time (i.e., because it is trapped in a loop or lost). There are eight
selectable timeout periods. This function can be disabled.
The SIM40 provides a timer to generate periodic interrupts. The periodic interrupt time
period can vary from 122 s to 15.94 s (with a 32.768-kHz crystal used to generate the
system clock). This function can be disabled.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68340 USER’S MANUAL
Go to: www.freescale.com
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