MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 364

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

8.4.2 Interrupt Register (IR)
The IR contains the priority level for the timer interrupt request and the 8-bit vector number
of the interrupt. The register can be read or written to at any time while in supervisor mode
and while the timer module is enabled (i.e., the STP bit in the MCR is cleared).
IR
Bits 15–11—Reserved
IL2–IL0—Interrupt Level Bits
IV7–IV0—Interrupt Vector Bits
8.4.3 Control Register (CR)
The CR controls the operation of the timer. The register can always be read or written
when the timer module is enabled (i.e., the STP bit in the MCR is cleared). Changing the
contents of the CR should only be attempted when the timer is disabled (the SWR bit in
the CR is cleared). Changing the CR while the timer is running may produce unpredictable
results.
CR
SWR—Software Reset
8-20
RESET:
RESET:
SWR
15
15
0
0
Each module that can generate interrupts has an interrupt level field. The priority level
encoded in these bits is sent to the CPU32 on the appropriate IRQ signal. The CPU32
uses this value to determine servicing priority. See Section 5 CPU32 for more
information.
Each module that can generate interrupts has an interrupt vector (IV) field. This 8-bit
number indicates the offset from the base of the vector table where the address of the
exception handler for the specified interrupt is located. The IV field is reset to $0F,
which indicates an uninitialized interrupt condition. See Section 5 CPU32 for more
information.
0
1 = Removes the software reset.
0 = A software reset is performed by first clearing this bit and then clearing the TO,
IE2
14
14
0
0
0
TG, and TC bits in the SR. The prescaler is loaded with $FF, the counter is set to
$0000, and the SR COM bit is cleared. When this bit is zero, the timer is
disabled.
IE1
13
13
0
0
0
IE0
12
12
0
0
0
TGE
11
11
Freescale Semiconductor, Inc.
0
0
0
For More Information On This Product,
PCLK
IL2
10
10
0
0
MC68340 USER’S MANUAL
Go to: www.freescale.com
CPE
IL1
9
0
9
0
CLK
IL0
8
0
8
0
POT2
IVR7
7
0
7
0
POT1
IVR6
6
0
6
0
POT0
IVR5
5
0
5
0
MODE2 MODE1 MODE0
IVR4
4
0
4
0
IVR3
3
1
3
0
Supervisor/User
Supervisor Only
IVR2
2
1
2
0
$604, $644
$606, $646
MOTOROLA
IVR1
OC1
1
1
1
0
IVR0
OC0
0
1
0
0