MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 64

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor, Inc.
If a system asserts DSACK for the required window around the falling edge of S2 and
obeys the proper bus protocol by maintaining DSACK (and/or BERR / HALT ) until and
throughout the clock edge that negates AS (with the appropriate asynchronous input hold
time), no wait states are inserted. The bus cycle runs at its maximum speed for bus cycles
terminated with DSACK (three clocks per cycle). When BERR (or BERR and HALT) is
asserted after DSACK , BERR (and HALT ) must meet the appropriate setup time prior to
the falling clock edge one clock cycle after DSACK is recognized. This setup time is
critical, and the MC68340 may exhibit erratic behavior if it is violated. When operating
synchronously, the data-in setup and hold times for synchronous cycles may be used
instead of the timing requirements for data relative to DS .
3.2.6 Fast Termination Cycles
With an external device that has a fast access time, the chip select circuit fast termination
enable (FTE) can provide a two-clock external bus transfer. Since the chip select circuits
are driven from the system clock, the bus cycle termination is inherently synchronized with
the system clock. Refer to Section 4 System Integration Module for more information on
chip selects.When fast termination is selected, the DD bits of the corresponding address
mask register are overridden. Fast termination can only be used with zero wait states. To
use the fast termination option, an external device should be fast enough to have data
ready, within the specified setup time, by the falling edge of S4. Figure 3-6 shows the
DSACK timing for a read with two wait states, followed by a fast termination read and
write. When using the fast termination option, DS is asserted only in a read cycle, not in a
write cycle.
*
*
S0
S1
S2
S3
SW
SW
SW
SW
S4
S5
S0
S1
S4
S5
S0
S1
S4
S5
S0
CLKOUT
AS
DS
R/W
DSACKx
D15–D0
FAST
TWO WAIT STATES IN READ
FAST
TERMINATION
TERMINATION
READ
WRITE
*
DSACKx only internally asserted for fast termination cycles.
Figure 3-6. Fast Termination Timing
MOTOROLA
MC68340 USER’S MANUAL
3- 15
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