MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 67

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

3.3.2 Write Cycle
During a write cycle, the MC68340 transfers data to memory or a peripheral device. Figure
3-8 is a flowchart of a word write cycle.
State 0—The write cycle starts in S0. During S0, the MC68340 places a valid address on
A31–A0 and valid function codes on FC3–FC0. The function codes select the address
space for the cycle. The MC68340 drives R/ W low for a write cycle. SIZ1/SIZ0 become
valid, indicating the number of bytes to be transferred.
State 1—One-half clock later during S1, the MC68340 asserts AS, indicating a valid
address on the address bus.
State 2—During S2, the MC68340 places the data to be written onto D15–D0, and
samples DSACK at the end of S2.
State 3—The MC68340 asserts DS during S3, indicating that data is stable on the data
bus. As long as at least one of the DSACK
(meeting the asynchronous input setup time requirement), the cycle terminates one clock
later. If DSACK is not recognized by the start of S3, the MC68340 inserts wait states
instead of proceeding to S4 and S5. To ensure that wait states are inserted, both
DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup
and hold times around the end of S2. If wait states are added, the MC68340 continues to
sample DSACK on the falling edges of the clock until one is recognized. The selected
device uses R/ W , SIZ1/SIZ0, and A0 to latch data from the appropriate byte(s) of D15–D8
and D7–D0. SIZ1/SIZ0 and A0 select the bytes of the data bus. If it has not already done
so, the device asserts DSACK to signal that it has successfully stored the data.
3-18
1. NEGATE DS AND AS
2. REMOVE DATA FROM D15–D0
1. SET R/W TO WRITE
2. DRIVE ADDRESS ON A31–A0
3. DRIVE FUNCTION CODE ON FC3–FC0
4. DRIVE SIZE PINS FOR OPERAND SIZE
5. ASSERT AS
6. PLACE DATA ON D15–D0
7. ASSERT DS
TERMINATE OUTPUT TRANSFER
START NEXT CYCLE
ADDRESS DEVICE
BUS MASTER
Figure 3-8. Word Write Cycle Flowchart
Freescale Semiconductor, Inc.
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signals is recognized by the end of S2
1. DECODE ADDRESS
2. LATCH DATA FROM D15–D0
3. ASSERT DSACKx SIGNALS
1. NEGATE DSACKx
TERMINATE CYCLE
ACCEPT DATA
SLAVE
MOTOROLA