MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 90

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

Figure 3-22 is a flowchart showing bus arbitration for a single device. This technique
allows processing of bus requests during data transfer cycles. Refer to Figures 3-23 and
3-24 for bus arbitration timing diagrams.
BR is negated at the time that BGACK is asserted. This type of operation applies to a
system consisting of the MC68340 and one device capable of bus mastership. In a system
having a number of devices capable of bus mastership, BR from each device can be wire-
ORed to the MC68340. In such a system, more than one bus request could be asserted
simultaneously. BG is negated a few clock cycles after the transition of BGACK . However,
if bus requests are still pending after the negation of BG , the MC68340 asserts another BG
within a few clock cycles after it was negated. This additional assertion of BG allows
external arbitration circuitry to select the next bus master before the current bus master
has finished using the bus. The following paragraphs provide additional information about
the three steps in the arbitration process. Bus arbitration requests are recognized during
normal processing, HALT assertion, and a CPU32 halt caused by a double bus fault.
MOTOROLA
Figure 3-22. Bus Arbitration Flowchart for Single Request
1. ASSERT BG
1. NEGATE BG (AND WAIT FOR
BGACK TO BE NEGATED)
RE-ARBITRATE OR RESUME
TERMINATE ARBITRATION
PROCESSOR OPERATION
GRANT BUS ARBITRATION
PROCESSOR
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68340 USER’S MANUAL
Go to: www.freescale.com
1. EXTERNAL ARBITRATION DETERMINES
2. NEXT BUS MASTER WAITS FOR BGACK
3. NEXT BUS MASTER ASSERTS BGACK
4. BUS MASTER NEGATES BR
1. PERFORM DATA TRANSFERS (READ AND
1. NEGATE BGACK
1. ASSERT BR
NEXT BUS MASTER
TO BE NEGATED
TO BECOME NEW MASTER
WRITE CYCLES) ACCORDING TO THE
SAME RULES THE PROCESSOR USES
ACKNOWLEDGE BUS MASTERSHIP
OPERATE AS BUS MASTER
RELEASE BUS MASTERSHIP
REQUESTING DEVICE
REQUEST THE BUS
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