MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 317

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

IVR7–IVR0—Interrupt Vector Bits
7.4.1.4 MODE REGISTER 1 (MR1). MR1 controls some of the serial module
configuration. This register can be read or written at any time when the serial module is
enabled (i.e., the STP bit in the MCR is cleared).
RxRTS—Receiver Request-to-Send Control
R/F—Receiver-Ready Select
7-22
Each module that generates interrupts has an interrupt vector field. This 8-bit number
indicates the offset from the base of the vector table where the address of the exception
handler for the specified interrupt is located. The IVR is reset to $0F, which indicates an
uninitialized interrupt condition. See Section 5 CPU32 for more information.
This feature can be used for flow control to prevent overrun in the receiver by using the
RTS output to control the CTS input of the transmitting device. If both the receiver
and transmitter are programmed for RTS control, RTS control will be disabled for both
since this configuration is incorrect. See 7.4.1.17 Mode Register 2 for information on
programming the transmitter RTS control.
1 = Upon receipt of a valid start bit, RTS is negated if the channel's FIFO is full.
0 = RTS is asserted by setting bit 1 or 0 in the OP and negated by clearing bit 1 or
1 = Bit 5 for channel B and bit 1 for channel A in the ISR reflect the channel FIFO full
0 = Bit 5 for channel B and bit 1 for channel A in the ISR reflect the channel receiver-
RTS is reasserted when the FIFO has an empty position available.
0 in the OP.
status. These ISR bits are set when the receiver FIFO is full and are cleared
when a position is available in the FIFO.
ready status. These ISR bits are set when a character has been received and are
cleared when the CPU32 reads the receive buffer.
IVR
Read /Write
MR1A, MR1B
Read/Write
RESET:
RESET:
RxRTS
IVR7
Freescale Semiconductor, Inc.
7
0
7
0
For More Information On This Product,
IVR6
R/F
6
0
6
0
MC68340 USER’S MANUAL
Go to: www.freescale.com
IVR5
ERR
5
0
5
0
IVR4
PM1
4
0
4
0
IVR3
PM0
3
1
3
0
Supervisor/User
Supervisor Only
IVR2
PT
2
1
2
0
$710, $718
IVR1
B/C1
1
1
1
0
$705
B/C0
IVR0
0
1
0
0
MOTOROLA