MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 390

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

10.1.2 Concurrent Operation Support
MOTOROLA
that provide the optimum performance for a given system. If the coprocessor
The M68000 coprocessor interface also facilitates the design of coprocessors.
The coprocessor designer must only conform to the coprocessor interface
that coprocessor. This provides a great deal of freedom in the implementation
The M68000 coprocessor interface provides full support of all operations
for implementing this concurrency while maintaining a programming model
uses the synchronous bus interface all coprocessor signals and data must
be synchronized with the main processor clock. Both the MC68881 and
and does not need an extensive knowledge of the architecture of the main
of a given coprocessor.
The programmer's model for the M68000 Family of microprocessors is based
on sequential, nonconcurrent instruction execution. This implies that the
which they occur. To maintain a uniform programmer's model, any copro-
cessor extensions should also maintain the model of sequential, noncon-
current instruction execution at the user level. Consequently, the programmer
can assume that the images of registers and memory affected by a given
instruction have been updated when the next instruction in the sequence
accessing these registers or memory locations is executed.
ciated coprocessors. Although the M68000 coprocessor interface allows con-
currency in coprocessor execution, the coprocessor designer is responsible
or alter resources to be altered or used by instruction "A", instruction "B"
can be executed concurrently (if the execution hardware is also available).
Thus, the required instruction interdependencies and sequences of the pro-
gram are always respected. The MC68882 coprocessor offers concurrent in-
struction execution while the MC68881 coprocessor does not. However, the
execution in the MC68881.
MC68882 floating-point coprocessors use the asynchronous bus handshake
protocol.
processor. Also, the main processor can operate with a coprocessor without
having explicit provisions made in the main processor for the capabilities of
instructions in a given sequence must appear to be executed in the order in
necessary for nonconcurrent operation of the main processor and its asso-
based on sequential nonconcurrent instruction execution.
For example, if the coprocessor determines that instruction "B" does not use
MC68030 can execute instructions concurrently with coprocessor instruction
MC68030 USER'S MANUAL
10-3