MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 480

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
for data cache hits are printed in boldface type. These lines are used to
The f o l l o w i n g example assumes data cache hits. The lines that are corrected
calculate the instruction-cache-case execution time. References are to the
preceding rules.
4.
2
3.
*Corrected for data cache hits.
1.
operation t i m i n g s that include an operand fetch in the CCop (e.g.,
with the number of instruction accesses in the CC column for com-
Data cache hits cannot easily be accounted for in instruction and
BFFFO and CHK2). The effect of a data cache hit on such CCop's has
been ignored for computational purposes.
RMC cycles (e.g., TAS and CAS) are forced to miss on data cache
reads. Therefore, a data cache hit has no effect on these instructions.
It is helpful to include the number of operand reads and writes along
puting the effect of data cache hits on execution time.
TAS (A3) +
ADD.L -(A1),D1
AND.L DI,([A2])
MOVE.L (A6),(8,A1)
fea - (An)
fea (An)
*Cea (An) +
Fetch Effective Address
"1c
*ADD EA,Dn
*la & 2 fea ([B])
*AND Dn,EA
* l b
*MOVE Source, (d16,An)
*TAS Mem
MC68030 USER'S MANUAL
2.
3.
4.
1.
A N D . L
TAS
A D D . L
MOVE.L
Instruction
NOTE
N O T E
DI,([A2])
(A6),(8,A1)
(A3)
-(A1),D1
Head
4
0
0
2
2
0
0
1
2
1
2 - 1
1 - 1
Tail
0
0
0
0
0
1
0
1
4 - 1(1/0/0)
3 - 1(1/00)
10(2/0/0)
12(1/0/1)
4(0/0/1)
2(0/0/0)
3(1/0/0)
2(0/0/1)
3(0/0/1)
2(1/0/0)
CC
11-17
I I