MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 392

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
10.1.4 Coprocessor S y s t e m Interface
10.1.4.1 COPROCESSOR CLASSIFICATION. M68000 coprocessors can be classi-
terface to communicate status and service requests to the main processor
through these registers. The coprocessor interface registers (CIRs) are also
The CIR set, response primitives, and format codes are discussed in 11).3
fied into two categories depending on their bus interface capabilities. The
first category, non-DMA coprocessors, consists of coprocessors that always
from the coprocessor by reading the operand from the appropriate CIR and
then writing the operand to a specified effective address with the appropriate
face circuitry of a coprocessor operating as a bus slave is not as complex as
that of a device operating as a bus master.
The encoding of bits 0-8 of the coprocessor instruction operation word is
dependent on the particular instruction being implemented (see 10.2 CO-
The communication protocol between the main processor and coprocessor
cessor. By accessing one of these interface registers, the MC68030 hardware
used to pass operands between the main processor and the coprocessor.
COPROCESSOR INTERFACE REGISTER SET and 10.4 COPROCESSOR RE-
SPONSE PRIMITIVES.
operate as bus slaves. The second category, DMA coprocessors, consists of
coprocessors that operate as bus slaves while communicating with the main
processor across the coprocessor interface, but also have the ability to op-
erate as bus masters, directly controlling the system bus.
available bus bandwidth or has special requirements not directly satisfied
a non-DMA coprocessor. Since non-DMA coprocessors always operate as
are performed by the main processor. The main processor transfers operands
address space specified on the function code lines. Likewise, the main pro-
cessor transfers operands to the coprocessor by reading the operand from
a specified effective address (and address space) and then writing that op-
erand to the appropriate CIR using the coprocessor interface. The bus inter-
PROCESSOR INSTRUCTION TYPES).
necessary to execute a coprocessor instruction uses a group of interface
registers, called coprocessor interface registers, resident within the copro-
initiates coprocessor instructions. The coprocessor uses a set of response
primitive codes and format codes defined for the M68000 coprocessor in-
If the operation of a coprocessor does not require a large portion of the
by the main processor, that coprocessor can be efficiently implemented as
bus slaves, all external bus-related functions that the coprocessor requires
MC68030 USER'S MANUAL
10-5
1(