MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 552

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

12,5.3 A 3-1-1-1 Burst Mode Memory Bank Using SRAMs
MOTOROLA
wishes to include some type of enable circuitry to take advantage of low bus
The fourth and last section of the memory bank is the address and data
74F244s are also acceptable. Two inputs to the address buffers remain unused
devices when SRAMs of suitable density become available. The RDCS signal,
qualified with AS, controls the data buffers during read operations. The ad-
dress buffers are always enabled.
circuitry to control CBACK and thus prevent or discontinue a burst cycle is
a simple addition. The circuitry should have two functions: to prevent wrap-
around and to prevent bursting when a data operand crosses a long-word
will all systems be able to afford the fast devices of this design. If the clock
frequency is below approximately 17.5 MHz, the same support logic supports
2-1-1-1 burst cycles with 35-ns memory. If 20 MHz is still the frequency of
choice, the designer may choose to run 3-1-1-1 burst cycles.
utilization, the timing in this design will be preserved if the memory's E signal
is asserted within 13 ns after the falling edge of state SO.
buffers. The address buffers are shown as 74ALS244s, but 74AS244s and
allowing the possibility for expansion up to 1 Mbyte without any additional
Some modifications to this design can improve performance. Specifically,
boundary.
Not all systems require the performance of 20-MHz 2-1-1-1 burst cycles, nor
Figure 12-15 shows the complete 3-1-1-1 memory bank with 256K bytes that
can operate with a 20-MHz MC68030. The required parts include:
(32) 64K × 1 SRAMs 35-ns access time (Motorola's MCM6287-35 or equiv-
(4)
(4)
(2)
(4)
(1)
(1)
(2)
74ALS244 buffers
74F374 latches
74F32 OR gates
74F191 counters
flip-flop
PAL16L8D (or equivalent)
inverters
alent)
MC68030 USER'S MANUAL
12-27
1: