MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 439

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

10
10-52
10.4.15 Transfer Multiple Main Processor Registers Primitive
10.4.16 Transfer Multiple Coprocessor Registers Primitive
IcAI
The transfer multiple main processor registers primitive transfers long-word
tion and the coprocessor. This primitive applies to general category instruc-
operands between one or more of its data or address registers and the
coprocessor, This primitive applies to general and conditional category in-
structions. Figure 10-35 shows the format of the transfer multiple main pro-
cessor registers primitive.
This primitive uses the CA, PC, and DR bits as previously described. If the
When the main processor receives this primitive, it reads a 16-bit register
transfers. If DR = 1, the main processor reads a long-word operand from the
operand CIR into each register indicated in the register select mask. The
transfer indicated by the DR bit.
The transfer multiple coprocessor registers primitive transfers from 0-16
operands between the effective address specified in the coprocessor instruc-
coprocessor issues this primitive with CA=0 during a conditional category
cessing.
select mask from the register select CIR. The format of the register select
mask is shown in Figure 10-36. A register is transferred if the bit correspond-
ing to the register in the register select mask is set to one. The selected
registers are transferred in the order D0-D7 and then A0-A7.
If DR=0, the main processor writes the contents of each register indicated
in the register select mask to the operand CIR using a sequence of long-word
registers are transferred in the same order, regardless of the direction of
instruction, the main processor initiates protocol violation exception pro-
Figure 10-35. Transfer Multiple Main Processor Registers Primitive Format
A7
15
15
14
A6
14
Pcl°RI ° I ° I 1 I 1 I ° I ° I ° I ° I ° I ° I ° I
A5
13
13
12
12
A4
Figure 10-36. Register Select Mask Format
A3
11
11
MC68030 USER'S MANUAL
A2
10
10
A1
9
9
A0
8
8
D7
7
7
D6
6
6
D5
5
5
D4
4
4
D3
3
3
D2
2
MOTOROLA
D1
2
1
DO
1
0
0