MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 449

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

IO
10.5.1
10-62
.1 COPROCESSOR-DETECTED PROTOCOL VIOLATIONS.
A coprocessor can detect protocol violations in various ways. According to
the M68000 coprocessor interface protocol, the main processor always ac-
coprocessor. That is, the main processor accesses these five registers in a
certain sequence, and the coprocessor expects them to be accessed in that
violation if the main processor accesses any of these five registers when the
According to the M68000 coprocessor interface protocol, the main processor
can perform a read of either the save or response CIRs or a write of either
the restore or control CIRs asynchronously with respect to the operation of
the coprocessor. That is, an access to one of these registers without the
Although the coprocessor can anticipate certain accesses to the restore, re-
sponse, and control coprocessor interface registers, these registers can be
The coprocessor cannot signal a protocol violation to the main processor
The main philosophy of the coprocessor-detected protocol violation is that
the coprocessor should always acknowledge an access to one of its interface
the main processor next reads the response CIR. If the coprocessor fails to
exceptions are communication failures between the main processor and co-
protocol violations occur when the main processor accesses entries in the
coprocessor interface register set in an unexpected sequence. The sequence
of operations that the main processor performs for a given coprocessor
cesses the operation word, operand, register select, instruction address, or
operand address CIRs synchronously with respect to the operation of the
sequence. As a minimum, all M68000 coprocessors should detect a protocol
coprocessor is expecting an access to either the command or condition CIR.
Likewise, if the coprocessor is expecting an access to the command or con-
dition CIR and the main processor accesses one of these five registers, the
coprocessor should detect and signal a protocol violation.
coprocessor explicitly expecting that access at that point can be a valid access.
accessed at other times also.
during the execution of cpSAVE or cpRESTORE instructions. If a coprocessor
detects a protocol violation during the cpSAVE or cpRESTORE instruction, it
should signal the exception to the main processor when the next coprocessor
assert DSACKx, to the main processor and signal a protocol violation when
processor across the M68000 coprocessor interface. Coprocessor-detected
instruction or coprocessor response primitive has been described previously
in this section.
instruction is initiated.
registers. If the coprocessor determines that the access is not valid, it should
MC68030 USER'S MANUAL
Protocol violation
MOTOROLA