DP83901AV National Semiconductor, DP83901AV Datasheet

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... Mbit sec Also included is a collision detect translator and diagnostic loopback capability 1 0 System Diagram TRI-STATE is a registered trademark of National Semiconductor Corporation C 1995 National Semiconductor Corporation TL F 10469 Features Compatible with IEEE 802 3 ...

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... PACKET TRANSMISSION 9 0 REMOTE DMA 10 0 INTERNAL REGISTERS 11 0 INITIALIZATION PROCEDURE 12 0 LOOPBACK DIAGNOSTICS 13 0 BUS ARBITRATION 14 0 PRELIMINARY ELECTRICAL CHARACTERISTICS 15 0 SWITCHING CHARACTERISTICS TIMING TEST CONDITIONS 17 0 PHYSICAL DIMENSIONS Top View Order Number DP83901AV See NS Package Number V68A 10469– 2 ...

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Pin Description Pin No Pin Name I O BUS INTERFACE PINS 2 PRD O PORT READ Enables data from external latch on to local bus during a memory write cycle to local memory (remote write operation) This allows asynchronous transfer ...

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Pin Description (Continued) Pin No Pin Name I O BUS INTERFACE PINS (Continued) 39 PRQ ADS1 O Z PORT REQUEST ADDRESS STROBE 1 32-BIT MODE If LAS is set in the Data Configuration Register this line is programmed as ADS1 ...

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Pin Description (Continued) Pin No Pin Name I O POWER SUPPLY PINS DIGITAL POSITIVE 5V SUPPLY PINS GND DIGITAL NEGATIVE (GROUND) SUPPLY PINS It is suggested that a decoupling capacitor be ...

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Functional Description ENCODER DECODER (ENDEC) MODULE The ENDEC consists of four main logical blocks a) The Manchester encoder accepts NRZ data from the controller encodes the data to Manchester and trans- mits it differentially to the transceiver through ...

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Functional Description col Control Logic Each destination address is also checked for all 1’s which is the reserved broadcast address FIFO AND BUS OPERATIONS Overview To accommodate the different rates at which data comes from (or goes to) ...

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Transmit Receive Packet Encapsulation Decapsulation A standard IEEE 802 3 packet consists of the following fields preamble Start of Frame Delimiter (SFD) destination address source address length data and Frame Check Sequence (FCS) The typical format is shown ...

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Direct Memory Access Control (DMA) The DMA capabilities of the SNIC greatly simplify the use of the DP83901A in typical configurations The local DMA channel transfers data between the FIFO and memory On transmission the packet is DMA’d ...

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Packet Reception The Local DMA receive channel uses a Buffer Ring Struc- ture comprised of a series of contiguous fixed length 256-byte (128 word) buffers for storage of received packets The location of the Receive Buffer Ring is ...

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Packet Reception (Continued) INITIALIZATION OF THE BUFFER RING Two static registers and two working registers control the operation of the Buffer Ring These are the Page Start Reg- ister Page Stop Register (both described previously) the Current Page ...

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Packet Reception (Continued) LINKING RECEIVE BUFFER PAGES If the length of the packet exhausts the first 256-byte buffer the DMA performs a forward link to the next buffer to store the remainder of the packet For a maximal ...

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Packet Reception (Continued) Buffer Ring Overflow If the Buffer Ring has been filled and the DMA reaches the Boundary Pointer Address reception of the incoming pack- et will be aborted by the SNIC Thus the packets previously received ...

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Packet Reception (Continued) Overflow Routine Flow Chart 10469 – 52 ...

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Packet Reception (Continued) Enabling the SNIC On An Active Network After the SNIC has been initialized the procedure for dis- abling and then re-enabling the SNIC on the network is simi- lar to handling Receive Buffer Ring overflow ...

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Packet Reception (Continued) BUFFER RECOVERY FOR REJECTED PACKETS If the packet is a runt packet or contains CRC or Frame Alignment errors it is rejected The buffer management log- ic resets the DMA back to the first buffer ...

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Packet Reception (Continued) REMOVING PACKETS FROM THE RING Packets are removed from the ring using the Remote DMA or an external device When using the Remote DMA the Send Packet command can be used This programs the Re- ...

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Packet Transmission The Local DMA is also used during transmission of a pack- et Three registers control the DMA transfer during trans- mission a Transmit Page Start Address Register (TPSR) and the Transmit Byte Count Registers (TBCR0 1) ...

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Remote DMA The Remote DMA channel is used to both assemble pack- ets for transmission and to remove received packets from the Receive Buffer Ring It may also be used as a general purpose slave DMA channel for ...

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Internal Registers All registers are 8-bit wide and mapped into four pages which are selected in the Command Register (PS0 PS1) Pins RA0–RA3 are used to address registers within each page Page 0 registers are those registers which ...

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Internal Registers (Continued) Page 1 Address Assignments (PS1 0 PS0 e RA0 –RA3 RD 00H Command (CR) Command (CR) 01H Physical Address Physical Address Register 0 (PAR0) Register 0 (PAR0) 02H Physical Address Physical Address Register 1 (PAR1) ...

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Internal Registers (Continued REGISTER DESCRIPTIONS COMMAND REGISTER (CR) 00H (READ WRITE) The Command Register is used to initiate transmissions enable or disable Remote DMA operations and to select register pages To issue a command the microprocessor ...

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Internal Registers (Continued REGISTER DESCRIPTIONS (Continued) INTERRUPT STATUS REGISTER (ISR) This register is accessed by the host processor to determine the cause of an interrupt Any interrupt can be masked in the Interrupt Mask Register (IMR) ...

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Internal Registers (Continued REGISTER DESCRIPTIONS (Continued) INTERRUPT MASK REGISTER (IMR) 0FH (WRITE) The Interrupt Mask Register is used to mask interrupts Each interrupt mask bit corresponds to a bit in the Interrupt Status Register (ISR) If ...

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Internal Registers (Continued REGISTER DESCRIPTIONS (Continued) DATA CONFIGURATION REGISTER (DCR) This Register is used to program the SNIC for 8- or 16-bit memory interface select byte ordering in 16-bit applications and establish FIFO thresholds The DCR ...

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Internal Registers (Continued REGISTER DESCRIPTIONS (Continued) TRANSMIT CONFIGURATION REGISTER (TCR) The transmit configuration establishes the actions of the transmitter section of the SNIC during transmission of a packet on the network LB1 and LB0 which select ...

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Internal Registers (Continued REGISTER DESCRIPTIONS (Continued) TRANSMIT STATUS REGISTER (TSR) 04H (READ) This register records events that occur on the media during transmission of a packet It is cleared when the next transmission is initiated by ...

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Internal Registers (Continued REGISTER DESCRIPTIONS (Continued) RECEIVE CONFIGURATION REGISTER (RCR) This register determines operation of the SNIC during reception of a packet and is used to program what types of packets to accept 7 Bit Symbol ...

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Internal Registers (Continued REGISTER DESCRIPTIONS (Continued) RECEIVE STATUS REGISTER (RSR) 0CH (READ) This register records status of the received packet including information on errors and the type of address match either physical or multicast The contents ...

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Internal Registers (Continued DMA REGISTERS The DMA Registers are partitioned into groups Transmit Receive and Remote DMA Registers The Transmit regis- ters are used to initialize the Local DMA Channel for trans- mission of packets while ...

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Internal Registers (Continued LOCAL DMA RECEIVE REGISTERS PAGE START AND STOP REGISTERS (PSTART PSTOP) The Page Start and Page Stop Registers program the start- ing and stopping address of the Receive Buffer Ring Since the SNIC ...

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Internal Registers (Continued) cant bits of the CRC generator are latched These 6 bits are then decoded decode to index a unique filter bit (FB0 –63) in the multicast address registers If the ...

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Initialization Procedures The SNIC must be initialized prior to transmission or recep- tion of packets from the network Power on reset is applied to the SNIC’s reset pin This clears sets the following bits Register Reset Bits Command ...

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Loopback Diagnostics To initiate a loopback the user first assembles the loopback packet then selects the type of loopback using the Transmit Configuration register bits LB0 LB1 The transmit configura- tion register must also be set to enable ...

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Loopback Diagnostics 3 Verify that the Address Recognition Logic can a) Recognize address match packets b) Reject packets that fail to match an address LOOPBACK OPERATION IN THE SNIC Loopback is a modified form of transmission using only ...

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Loopback Diagnostics Since errored packets can be rejected the status associat- ed with these packets is lost unless the CPU can access the Receive Status Register before the next packer arrives In situations where another packet arrives very ...

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Bus Arbitration and Timing The SNIC operates in three possible modes BUS MASTER (WHILE PERFORMING DMA) BUS SLAVE (WHILE BEING ACCESSED BY CPU) IDLE Upon power-up the SNIC indeterminate state After receiving a hardware reset ...

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Bus Arbitration and Timing Note In 32-bit address mode ADS1 is at TRI-STATE after the first T1–T4 states thus pull-down resistor is required for 32-bit address (Continued) 16-Bit Address 16-Bit Data 32-Bit Address 8-Bit Data ...

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Bus Arbitration and Timing When in 32-bit mode four additional BSCK cycles are re- quired per burst The first bus cycle (T1 – each burst is used to output the upper 16-bit addresses This 16-bit ...

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Bus Arbitration and Timing FIFO AT THE BEGINNING OF RECEIVE At the beginning of reception the SNIC stores entire Ad- dress field of each incoming packet in the FIFO to deter- mine whether the packet matches its Physical ...

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Bus Arbitration and Timing Threshold Detection (Bus Latency) To assure that no overwriting of data in the FIFO occurs the FIFO logic flags a FIFO overrun as the 13th byte is written into the FIFO effectively shortening the ...

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Bus Arbitration and Timing REMOTE DMA-BIDIRECTIONAL PORT CONTROL The Remote DMA transfers data between the local buffer memory and a bidirectional port (memory transfer) This transfer is arbited on a byte by byte basis versus ...

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Bus Arbitration and Timing REMOTE WRITE TIMING A Remote Write operation transfers data from the I O port to the local buffer RAM The SNIC initiates a transfer by requesting a byte word via the PRQ The system ...

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Bus Arbitration and Timing Note The dashed lines indicate incorrect timing as described in the text FIGURE 9 Timing Diagram for Dummy Remote Read Write operation could be corrupted This is shown by the hatched waveforms in the ...

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Bus Arbitration and Timing SLAVE MODE TIMING When CS is low the SNIC becomes a bus slave The CPU can then read or write any internal registers All register access is byte wide The timing for register access ...

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... Preliminary Electrical Characteristics Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage ( Input Voltage ( Output Voltage ( OUT Storage Temperature Range ( STG Power Dissipation (PD) Lead Temp (TL) (Soldering 10 sec ) ...

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Preliminary Electrical Characteristics Preliminary DC Specifications Symbol Parameter DIFFERENTIAL PINS (TX RX and Diff Output Voltage ( Diff Output Voltage Imbalance ( Undershoot Voltage ( ...

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Switching Characteristics Symbol Parameter rss Register Select Setup to ADS0 Low rsh Register Select Hold from ADS0 Low aswi Address Strobe Width In ackdv Acknowledge Low to Data Valid rdz Read Strobe to Data TRI-STATE (Note 3) rackl ...

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Switching Characteristics Register Read (Non-Latched ADS0 Symbol Parameter rsrs Register Select to Read Setup (Notes 1 3) rsrh Register Select Hold from Read ackdv ACK Low to Valid Data rdz Read Strobe to Data TRI-STATE (Note 2) rackl ...

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Switching Characteristics Symbol Parameter rss Register Select Setup to ADS0 Low rsh Register Select Hold from ADS0 Low aswi Address Strobe Width In rwds Register Write Data Setup rwdh Register Write Data Hold ww Write Strobe Width from ...

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Switching Characteristics Register Write (Non-Latched ADS0 Symbol Parameter rsws Register Select to Write Setup (Note 1) rswh Register Select Hold from Write rwds Register Write Data Setup rwdh Register Write Data Hold wackl Write Low to ACK Low ...

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Switching Characteristics Symbol Parameter brqhl Bus Clock to Bus Request High for Local DMA brqhr Bus Clock to Bus Request High for Remote DMA brql Bus Request Low from Bus Clock backs Acknowledge Setup to Bus Clock (Note ...

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Switching Characteristics Symbol Parameter bcyc Bus Clock Cycle Time (Note 2) bch Bus Clock High Time bcl Bus Clock Low Time bcash Bus Clock to Address Strobe High bcasl Bus Clock to Address Strobe Low aswo Address Strobe ...

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Switching Characteristics Symbol Parameter bcrl Bus Clock to Read Strobe Low bcrh Bus Clock to Read Strobe High ds Data Setup to Read Strobe High dh Data Hold from Read Strobe High drw DMA Read Strobe Width Out ...

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Switching Characteristics Symbol Parameter bcwl Bus Clock to Write Strobe Low bcwh Bus Clock to Write Strobe High wds Data Setup to WR High wdh Data Hold from WR Low waz Write Strobe to Address TRI-STATE (Notes 1 ...

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Switching Characteristics Symbol Parameter ews External Wait Setup to T3 0Clock (Note 1) ewr External Wait Release Time (Note 1) Note 1 The addition of wait states affects the count of deserialized bytes and is limited to a ...

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Switching Characteristics Symbol Parameter bpwrl Bus Clock to Port Write Low bpwrh Bus Clock to Port Write High prqh Port Write High to Port Request High (Note 1) prql Port Request Low from Read Acknowledge High rakw Remote ...

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Switching Characteristics Remote DMA (Read Send Command) Recovery Time Symbol Parameter bpwrl Bus Clock to Port Write Low bpwrh Bus Clock to Port Write High prqh Port Write High to Port Request High (Note 1) prql Port Request ...

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Switching Characteristics Symbol Parameter bprqh Bus Clock to Port Request High (Note 1) wprql WACK to Port Request Low wackw WACK Pulse Width bprdl Bus Clock to Port Read Low (Note 2) bprdh Bus Clock to Port Read ...

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Switching Characteristics Remote DMA (Write Cycle) Recovery Time Symbol Parameter bprqh Bus Clock to Port Request High (Note 1) wprql WACK to Port Request Low wackw WACK Pulse Width bprdl Bus Clock to Port Read Low (Note 2) ...

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Switching Characteristics TRANSMIT SPECIFICATIONS (End of Packet) Symbol Parameter t Transmit Output High before Idle (Half Step) TOH t Transmit Output Idle Time to TOI Symbol Parameter rstw Reset Pulse Width (Note 1) Note 1 The RESET pulse ...

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