DP83901AV National Semiconductor, DP83901AV Datasheet - Page 45

• Manufacturer Part Number: DP83901AV
• Description: IC CONTROLLR SER NETWK IN 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP83901AV

• Controller Type: Serial Network Interface Controller
• Interface: Serial
• Voltage - Supply: 5V
• Current - Supply: 110mA
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Operating Temperature: -
• Other names: *DP83901AV

13 0 Bus Arbitration and Timing
SLAVE MODE TIMING
When CS is low the SNIC becomes a bus slave The CPU
can then read or write any internal registers All register
access is byte wide The timing for register access is shown
below The host CPU accesses internal registers with four
address lines RA0–RA3 SRD and SWR strobes
TIME BETWEEN CHIP SELECTS
The SNIC requires that successive chip selects be no closer
than 4 bus clocks (BSCK) together If the condition is violat-
ed the SNIC may glitch ACK CPUs that operate from pipe-
lined instructions (i e 386) or have a cache (i e 486) can
Time between Chip Selects
Read from Register
(Continued)
Write to Register
45
ADS0 is used to latch the address when interfacing to a
multiplexed address data bus Since the SNIC may be a
local bus master when the host CPU attempts to read or
write to the controller an ACK line is used to hold off the
CPU until the SNIC leaves master mode Some number of
BSCK cycles is also required to allow the SNIC to synchro-
nize to the read or write cycles
execute consecutive I O cycles very quickly The solution is
to delay the execution of consecutive I O cycles by either
breaking the pipeline or forcing the CPU to access outside
its cache
TL F 10469 – 58
TL F 10469 – 30
TL F 10469 – 31