DP83901AV National Semiconductor, DP83901AV Datasheet - Page 40

• Manufacturer Part Number: DP83901AV
• Description: IC CONTROLLR SER NETWK IN 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP83901AV

• Controller Type: Serial Network Interface Controller
• Interface: Serial
• Voltage - Supply: 5V
• Current - Supply: 110mA
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Operating Temperature: -
• Other names: *DP83901AV

5 The SNIC holds onto the bus for the entire sequence The
13 0 Bus Arbitration and Timing
FIFO AT THE BEGINNING OF RECEIVE
At the beginning of reception the SNIC stores entire Ad-
dress field of each incoming packet in the FIFO to deter-
mine whether the packet matches its Physical Address Reg-
ister or maps to one of its Multicast Registers This causes
the FIFO to accumulate 8 bytes Furthermore there are
some synchronization delays in the DMA PLA Thus the
actual time that BREQ is asserted from the time the Start of
Frame Delimiter (SFD) is detected is 7 8 s This operation
affects the bus latencies at 2 byte and 4 byte thresholds
during the first receive BREQ since the FIFO must be filled
to 8 bytes (or 4 words) before issuing a BREQ
FIFO Operation at the End of Receive
When Carrier Sense goes low the SNIC enters its end of
packet processing sequence emptying its FIFO and writing
the status information at the beginning of the packet Figure
longest time BREQ may be extended occurs when a packet
ends just as the SNIC performs its last FIFO burst The
SNIC in this case performs a programmed burst transfer
followed by flushing the remaining bytes in the FIFO and
completes by writing the header information to memory The
following steps occur during this sequence
1 SNIC issues BREQ because the FIFO threshold has been
2 During the burst packet ends resulting in BREQ extend-
3 SNIC flushes remaining bytes from FIFO
4 SNIC performs internal processing to prepare for writing
5 SNIC writes 4-byte (2-word) header
6 SNIC deasserts BREQ
End of Packet Processing (EOPP) times for 10 MHz and
20 MHz have been tabulated below
reached
ed
the header
End of Packet Processing
TL F 10469–53
(Continued)
40
Mode
Byte
Byte
Word
Word
End of Packet Processing Times for Various FIFO
Thresholds Bus Clocks and Transfer Modes
Maximum Bus Latency for Word Mode
Maximum Bus Latency for Byte Mode
Threshold
2 bytes
4 bytes
8 bytes
2 bytes
4 bytes
8 bytes
2 bytes
4 bytes
8 bytes
2 bytes
4 bytes
8 bytes
Bus Clock
10 MHz
20 MHz
10 MHz
20 MHz
TL F 10469 – 54
TL F 10469 – 55
11 0 s
EOPP
7 0 s
8 6 s
3 6 s
4 2 s
5 0 s
5 4 s
6 2 s
7 4 s
3 0 s
3 2 s
3 6 s