PEB22504HT-V11 Infineon Technologies, PEB22504HT-V11 Datasheet - Page 40

• Manufacturer Part Number: PEB22504HT-V11
• Description: IC INTERFACE QUAD 100-TQFP
• Manufacturer: Infineon Technologies

Specifications of PEB22504HT-V11

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 100-LFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB22504HT-V11; PEB22504HT-V11IN

• Recovery:
4.1.9
The internal PLL (Phase-Locked Loop) circuitry called DCO (Digitally Controlled
Oscillator) generates a “jitter-free“ output clock which is directly depending on the phase
difference between the incoming clock and the jitter-attenuated clock. The jitter
attenuator can be placed on the receive or transmit path of each channel individually.
The working clock is an internally generated high-frequency clock based on the clock
provided on pin MCLK. The jitter attenuator meets the requirements of ITU-T I.431,
G.703, G.736-739, G.823, G.824, ETSI 300011, ETSI TBR12/13, AT&T TR62411, AT&T
TR43802, TR-TSY 009, TR-TSY 253 and TR-TSY 499. The receive jitter attenuator can
be synchronized either to the extracted receive clock RCLK, or to a 2.048 (E1)/1.544
MHz (T1/J1)/8 KHz (E1/T1/J1) clock provided on pin SYNC. The transmit jitter attenuator
synchronizes with either the clock provided on pin TCLK, or the receive clock RCLK
(remote loop/loop-timed).
Received data is written into the elastic buffer with RCLK and is read out with the de-
jittered clock sourced by DCO (if JATT in receive direction is selected). The jitter
attenuated clock can be output on pin RCLK. An 8-kHz clock is provided on pin FSC.
Transmit data is written into the elastic buffer with TCLK and is read out with the de-
jittered clock sourced by DCO (if JATT in transmit direction is selected). In the loop-timed
clock configuration (CMR.ELT) the DCO circuitry generates a transmit clock that is
frequency synchronized to RCLK.
The DCO circuitry attenuates the incoming jittered clock starting at 2 Hz (E1)/6 Hz
(T1 J1) jitter frequency with 20 dB/decade fall-off. Wander with a jitter frequency below
2/6 Hz is passed unattenuated. The intrinsic jitter in the absence of any input jitter is less
than 0.02 UI.
The DCO accepts gapped clocks, which are used in ATM or SDH/SONET applications.
For some applications, it might be useful to start jitter attenuation at lower frequencies.
Therefore the corner frequency is switchable by the factor of ten down to 0.2/0.6 Hz
(CMR.SCF).
Data Sheet
to 4096 pulse periods). ETS 300233, which requires detection intervals of at least
1 ms, can be fulfilled.
The recovery procedure starts after detection of a logical "one" (digital receive
interface) or a pulse (analog receive interface) with an amplitude more than Q dB
(defined by LIM2.RIL(2:0)) of the nominal pulse. The value in the 8 bit register PCR
defines the number of pulses (1 to 255) required to clear the LOS alarm. Additional
recovery conditions may be programmed by register LIM5.LOSR(1:0).
Jitter Attenuator
40
Interface Description
QuadLIU V1.1
PEB 22504
2001-02