PEB22504HT-V11 Infineon Technologies, PEB22504HT-V11 Datasheet - Page 94

• Manufacturer Part Number: PEB22504HT-V11
• Description: IC INTERFACE QUAD 100-TQFP
• Manufacturer: Infineon Technologies

Specifications of PEB22504HT-V11

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 100-LFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB22504HT-V11; PEB22504HT-V11IN

SLP
PDENI
AIS
LOS
Interrupt Status Register 1 (Read)
Addresses: 18
ISR1
All bits are reset when ISR1 is read.
If bit LIM4.VIS is set, interrupt statuses in ISR1 may be flagged although they are
masked via register IMR1. However, these masked interrupt statuses neither generate a
signal on INT, nor are they visible in register CIS.
LTC
Data Sheet
7
H
, 38
Slip Positive
The frequency of the receive route clock is less than the frequency of
the receive framer interface working clock, which is a multiple of or
equal to 2.048 MHz (E1) 1.544 MHz (T1/J1). Data is repeated. SLP is
also set during alarm simulation.
Pulse-Density Violation Interrupt
This bit is set if a pulse-density violation is detected(LSR0.PDEN = 1).
The bit is set during alarm simulation.
Alarm Indication Signal (Blue Alarm)
This bit is set when an alarm indication signal is detected and bit
LSR0.AIS is set. It is also set during alarm simulation.
If LIM4.SCI is set, this interrupt status bit is set with every change of
LSR0.AIS.
Loss-of-Signal (Red Alarm)
This bit is set when a loss-of-signal alarm is detected in the received
bit stream and LSR0.LOS is set. It is also set during alarm simulation.
If LIM4.SCI is set, this interrupt status bit is set with every change of
LSR0.LOS.
Loss of Transmit Clock
This bit is set when a loss of transmit clock is detected and bit
LSR1.TCS is set. It is also set during alarm simulation.
If LIM4.SCI is set, this interrupt status bit is set with every change of
LSR1.TCS.
H
, 58
H
, 78
H
94
LTC
Register Description
QuadLIU V1.1
SEC
0
PEB 22504
2001-02