PEB22504HT-V11 Infineon Technologies, PEB22504HT-V11 Datasheet - Page 41

• Manufacturer Part Number: PEB22504HT-V11
• Description: IC INTERFACE QUAD 100-TQFP
• Manufacturer: Infineon Technologies

Specifications of PEB22504HT-V11

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 100-LFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB22504HT-V11; PEB22504HT-V11IN

The jitter attenuator works in two different modes:
• Slave mode
• Master mode
Table 8
Table 8
Mode
Master
Master
Master
Master
Slave
Slave
Slave
Slave
Data Sheet
In slave mode (CMR.MAS = 0), the DCO is synchronized with the recovered route
clock. In case of LOS (receive mode) or transmit clock is lost (transmit mode, bit
LSR1.TCS = 1), the DCO switches to master mode automatically. If bit CMR.DCS is
set, automatic switching from RCLK/TCLK to SYNC is disabled.
In master mode (CMR.MAS = 1) the jitter attenuator is in free-running mode if no clock
is supplied on pin SYNC . If there is a clock with a frequency of 2.048 (E1)/1.544 MHz
(T1/J1)/8 kHz (E1/T1/J1) on the SYNC input, the DCO is synchronized with this input
signal.
In some applications, it might be useful to synchronize to a gapped clock sourced by
pin SYNC. In this case, the DCO circuitry would be centered to the nominal frequency.
Optionally the QuadLIU™ offers the ability to disable the centering the DCO circuitry
(LIM4.DCF = 1).
shows the clock modes with the corresponding synchronization sources.
Internal
LOS active
or
TCS set
no
no
no
no
no
no
no
yes
Clocking Modes
SYNC
Input
V
1.544 MHz Synchronized with SYNC input
2.048 MHz Synchronized with SYNC input
8 kHz
V
1.544 MHz Synchronized with line RCLK/TCLK(4:1),
2.048 MHz Synchronized with line RCLK/TCLK(4:1) ,
V
DD
DD
DD
DCO
Free-running (DCO centered)
GCR.SSF(1:0) = 01
GCR.SSF(1:0) = 00
Synchronized with SYNC input
GCR.SSF(1:0) = 10
Synchronized with line RCLK/TCLK(4:1),
selected by CMR.DSS(1:0)
selected by CMR.DSS(1:0)
selected by CMR.DSS(1:0)
Free running (DCO centered)
41
1)
Output Clock
Interface Description
2)
2)
2)
2)
QuadLIU V1.1
PEB 22504
2001-02