PEB22504HT-V11 Infineon Technologies, PEB22504HT-V11 Datasheet - Page 80

• Manufacturer Part Number: PEB22504HT-V11
• Description: IC INTERFACE QUAD 100-TQFP
• Manufacturer: Infineon Technologies

Specifications of PEB22504HT-V11

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 100-LFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB22504HT-V11; PEB22504HT-V11IN

Loop Code Register 1 (Read/Write)
Addresses: 0E
Value after reset: 40
LCR1
LDCL(1:0)
LACL(1:0)
XLD
1)
Data Sheet
Terms "Line Loop Back" (LLB) and "In Band Loop" (IBL) are synonyms.
LDCL1
7
H
, 2E
Length Deactivate (Down) Code
These bits defines the length of the user-programmable LLB
deactivate code, which is programmable in register LCR2.
00 = 5 bit
01 = 6 bit (default)
10 = 7 bit
11 = 8 bit
If a shorter pattern length is required, select a multiple of the required
length and repeat the pattern in LCR2.
Length Activate (Up) Code
These bits defines the length of the user-programmable LLB activate
code, which is programmable in register LCR3.
00 = 5 bit (default)
01 = 6 bit
10 = 7 bit
11 = 8 bit
If a shorter pattern length is required, select a multiple of the required
length and repeat the pattern in LCR3.
Transmit LLB Deactivate (Down) Code
0 =
1 =
LDCL0
H
H
, 4E
Normal operation (default)
Normal data is replaced by the LLB deactivation code
continuously until this bit is reset.
LCR1.XLA and LIM3.XPRBS must be cleared. LLB deactivate
code can be inserted in receive (LIM3.GTP = 0) or transmit
direction (LIM3.GTP = 1).
H
, 6E
LACL1
H
LACL0
1)
80
XLD
Register Description
QuadLIU V1.1
XLA
0
PEB 22504
2001-02