PEB22504HT-V11 Infineon Technologies, PEB22504HT-V11 Datasheet - Page 68

• Manufacturer Part Number: PEB22504HT-V11
• Description: IC INTERFACE QUAD 100-TQFP
• Manufacturer: Infineon Technologies

Specifications of PEB22504HT-V11

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 100-LFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB22504HT-V11; PEB22504HT-V11IN

EPRM
XPRBS
IPRBS
SPRBS
Line Interface Mode 4 (Read/Write)
Addresses: 05
Value after reset: 00
LIM4
RPE
TPE
VIS
Data Sheet
RPE
7
H
, 25
Enable PRBS Monitor
0 =
1 =
Transmit Pseudo-Random Bit Sequence (PRBS)
0 =
1 =
Invert Pseudo-Random Bit Sequence PRBS
0 =
1 =
Select Pseudo-Random Bit Sequence Algorithm
0 =
1 =
RCLK Positive Edge
0 =
1 =
Positive Sample Edge of TCLK
0 =
1 =
Masked Interrupts Visible
0 =
1 =
H
TPE
H
, 45
The PRBS monitor is disabled.
The PRBS monitor is enabled.
Normal transmit operation
A “1” in this bit position enables transmission of a pseudo-
random bit sequence. Depending on bit SPRBS, the PRBS is
generated according to 2
The generated PRBS data is not inverted.
The PRBS data is inverted.
Pseudo-random bit sequence algorithm: 2
Pseudo-random bit sequence algorithm: 2
14 consecutive zeros restriction.
RDOP/N are output with the falling edge of the RCLK clock.
RDOP/N are output with the rising edge of the RCLK clock.
XDIP/N are latched with the falling edge of the TCLK clock.
XDIP/N are latched with the rising edge of the TCLK clock.
Masked interrupt status bits are not visible in registers ISR(0:1).
Masked interrupt status bits are visible in ISR(0:1), but they are
not visible in register CIS. Interrupt request pin INT stays
inactive.
H
, 65
VIS
H
SCI
68
DCF
15
-1 or 2
PC2
20
-1 (ITU-T O.151).
PC1
Register Description
15
20
-1
-1 with maximum
QuadLIU V1.1
PC0
0
PEB 22504
2001-02