PEF82912FV1.4 Infineon Technologies, PEF82912FV1.4 Datasheet - Page 122

• Manufacturer Part Number: PEF82912FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PEF82912FV1.4

• Mounting Style: SMD/SMT
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

•
Figure 54
As can be seen from the transition criteria, combinations of multiple conditions are
possible as well. A “ ” stands for a logical AND combination. And a “+” indicates a logical
OR combination.
Test Signals
• 2 kHz Single Pulses (TM1)
• 96 kHz Continuous Pulses (TM2)
Note: The test signals TM1 and TM2 are invoked via C/I codes ‘TM1‘ and ‘TM2‘
External Layer-1 Statemachine
Instead of using the integrated layer-1 statemachine it is also possible to implement the
layer-1 statemachine completely in software.
The internal layer-1 statemachine can be disabled by setting the L1SW bit in the
S_CONF0 register to ’1’.
The transmitter is completely under control of the microcontroller via register S_CMD.
The status of the receiver is stored in register S_STA and has to be evaluated by the
microcontroller. This register is updated continuously. If not masked a RIC interrupt is
generated by any change of the register contents. The interrupt is cleared after a read
access to this register.
Reset States
After an active signal on the reset pin RST the S-transceiver state machine is in the reset
state.
Data Sheet
One pulse with a width of one bit period per frame with alternating polarity.
Continuous pulses with a pulse width of one bit period.
according to
State Diagram Notation
IOM-2 Interface
C/I code
S/T Interface
INFO
Chapter
2.5.5.1.
OUT
Ind. Cmd.
i
x
S ta te
IN
i
r
108
Unconditional
Transition
macro_17.vsd
Functional Description
PEF 82912/82913
2001-03-30