PEF82912FV1.4 Infineon Technologies, PEF82912FV1.4 Datasheet - Page 91

• Manufacturer Part Number: PEF82912FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PEF82912FV1.4

• Mounting Style: SMD/SMT
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

However, if the same filter is selected towards the state machine as programmed
towards the µC, the user has to be aware that if CRC mode is active, the state machine
is informed at the end of the next U-superframe.
2.4.5
Figure 42
M6 bit data:
Via the M4WMASK register the user can selectively program which M4 bits are
externally controlled and which are set by the internal state machine or dedicated pins
(PS1, PS2). If one M4WMASK bit is set to ’0’ then the M4 bit value in the U-transmit
frame is determined by the bit value at the corresponding bit position in the M4W register.
Note: By bit 6 in the M4WMASK register it can be selected whether SAI is set by the
Via the M4RMASK register the user can selectively program which M4 bit changes shall
cause an report to the µC.
The M4W register latches the M4 bits that are sent with the next available U-superframe.
The M4R register contains the last validated M4 bit data.
The default value of M51, M52 and M61 can be overwritten at any time by use of register
M56W. M56R latches the last received and verified M5, M6 bit data.
The control of the FEBE bit is performed by the CRC-Processor, see
Data Sheet
state machine or by µC access and whether the value of the received UOA bit is
reported to the state machine or UOA= ’1’ is signalled.
and
M4, M5, M6 Bit Control Mechanisms
Figure 43
show the control mechanisms that are provided for M4, M5 and
77
Functional Description
PEF 82912/82913
Chapter
2001-03-30
2.4.6.