PEF82912FV1.4 Infineon Technologies, PEF82912FV1.4 Datasheet - Page 187

• Manufacturer Part Number: PEF82912FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PEF82912FV1.4

• Mounting Style: SMD/SMT
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

4.9.9
IOM_CR
Value after reset: 08
SPU
TIC_DIS
EN_BCL
DIS_OD
DIS_IOM Disable IOM
Data Sheet
SPU
7
IOM_CR - Control Register IOM Data
Software Power UP
0 =
1 =
TIC Bus Disable
0 =
1 =
Enable Bit Clock BCL
0 =
1 =
Disable Open Drain
0 =
1 =
DIS_IOM should be set to ‘1’ if external devices connected to the IOM
interface should be “disconnected” e.g. for power saving purposes.
However, the Q-SMINT I internal operation is independent of the DIS_IOM
bit.
0
The DU line is normally used for transmitting data.
Setting this bit to ‘1’ will pull the DU line to low. This will enforce the
Q-SMINT I and other connected layer 1 devices to deliver IOM-
clocking.
The last octet of the last IOM time slot (TS 11) is used as TIC bus.
The TIC bus is disabled. The last octet of the last IOM time slot
(TS 11) can be used like any other time slot. This means that the
timeslots TIC, A/B, S/G and BAC are not available any more.
The BCL clock is disabled (output is high impedant)
The BCL clock is enabled
IOM outputs are open drain driver
IOM outputs are push pull driver
H
0
TIC_DIS EN_BCL
read/write
173
0
Register Description
PEF 82912/82913
DIS_OD DIS_IOM
Address:
2001-03-30
0
56
H