PEF82912FV1.4 Infineon Technologies, PEF82912FV1.4 Datasheet - Page 203

• Manufacturer Part Number: PEF82912FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PEF82912FV1.4

• Mounting Style: SMD/SMT
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

40kHz
4.11.14
The Loop register controls the digital loopbacks of the U-transceiver. The analog
loopback (No. 3) is closed by C/I= ‘ARL’.
Note: If the EOC automatic mode is selected (MFILT.EOC Filter = ’100’), then register
LOOP
Reset Value:
DLB
TRANS
Data Sheet
LOOP is accessed by the internal EOC processor:
EOC-command ’LB1’ (’LB2’) sets LOOP.U/IOM and LOOP.LB1 (LOOP.LB2)
EOC-command ’RTN’ resets LOOP.LB1, LOOP.LB2 and LOOP.LBBD
7
0
LOOP - Loop Back Register
1 =
40 kHz Test Signal
0 =
1 =
Close Framer/Deframer Loopback
– the loopback is closed at the analog/digital interface
– prerequisite is that LB1, LB2, LBBD and U/IOM
– only user data is looped and no maintenance data is looped back
0 =
1 =
Transparent/ Non-Transparent Loopback
– in transparent mode user data is both passed on and looped back,
– if LBBD, LB2, LB1 is closed towards the IOM
– bit TRANS has no effect on DLB and the analog loopback (ARL operates
whereas in non-transparent mode data is not forwarded but substituted
by ’1’s (idle code) and just looped back
set to ’0’ then the state machine has to be put into state ’Transparent’ first
(e.g. by C/I = DT) before data is output on the U-interface
always in transparent mode)
08
DLB
6
issues +/-1 pulses
issues single pulses in state ’Test’
issues a 40 kHz test signal in state ’Test’
H
Framer/Deframer loopback open
Framer/Deframer loopback closed
TRANS
5
U/IOM
4
read*
189
)
/write
1
3
2)
LBBD
®
interface and bit TRANS is
2
®
are set to ‘0’
Register Description
PEF 82912/82913
LB2
Address:
1
2001-03-30
1)
LB1
0
70
H